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    <title>topic LPC55S69 Ctimer CAP question in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Ctimer-CAP-question/m-p/1583791#M51290</link>
    <description>&lt;P&gt;1. Does Ctime CAP must triggered by external PIN? Could we use internal configure to measure some PINs frequency.&lt;/P&gt;&lt;P&gt;2. Does&amp;nbsp;LPC55S69 Ctimer CAP abality has limit? eg. I want use Ctimer CAP to measure 48KHZ clock.&lt;/P&gt;</description>
    <pubDate>Wed, 18 Jan 2023 08:31:45 GMT</pubDate>
    <dc:creator>qingyunliu</dc:creator>
    <dc:date>2023-01-18T08:31:45Z</dc:date>
    <item>
      <title>LPC55S69 Ctimer CAP question</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Ctimer-CAP-question/m-p/1583791#M51290</link>
      <description>&lt;P&gt;1. Does Ctime CAP must triggered by external PIN? Could we use internal configure to measure some PINs frequency.&lt;/P&gt;&lt;P&gt;2. Does&amp;nbsp;LPC55S69 Ctimer CAP abality has limit? eg. I want use Ctimer CAP to measure 48KHZ clock.&lt;/P&gt;</description>
      <pubDate>Wed, 18 Jan 2023 08:31:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Ctimer-CAP-question/m-p/1583791#M51290</guid>
      <dc:creator>qingyunliu</dc:creator>
      <dc:date>2023-01-18T08:31:45Z</dc:date>
    </item>
    <item>
      <title>Re: LPC55S69 Ctimer CAP question</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Ctimer-CAP-question/m-p/1585621#M51330</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206855"&gt;@qingyunliu&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. I did not understand if you are refering: how the capture is triggerd to get the value or how the input signal is provided to the mcu.&lt;/P&gt;&lt;P&gt;2. The CAP frequency limit is defined with the APB bus clock. On chapter 25.6.11 Count Control Register of the user manual says "the frequency of the CAP input cannot exceed one half of the&lt;BR /&gt;APB bus clock" also on chapter 4.4.1 Clock generation says "The maximum allowed frequency for main clock and system clock (to CPU0, CPU1, AHB bus, Sync, etc.) is 150 MHz".&lt;/P&gt;&lt;P&gt;I'll be waiting for the clarification to question 1.&lt;/P&gt;&lt;P&gt;Best Regards, Miguel.&lt;/P&gt;</description>
      <pubDate>Thu, 19 Jan 2023 16:52:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Ctimer-CAP-question/m-p/1585621#M51330</guid>
      <dc:creator>Miguel04</dc:creator>
      <dc:date>2023-01-19T16:52:00Z</dc:date>
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