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    <title>topic Re: Interrupt Priority in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Interrupt-Priority/m-p/1578080#M51197</link>
    <description>&lt;P&gt;In principle, you can do it anytime.&lt;/P&gt;&lt;P&gt;Just keep in mind that the architecture might have some delays/caches, so you need to add memory barriers, as explained in &lt;A href="https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/" target="_blank"&gt;https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;As for myself, I initialize interrupts during the device/peripheral setup, one by one, with the global interrupts disabled. At the end, with starting the application or the RTOS, the global interrupts get enabled.&lt;/P&gt;&lt;P&gt;If disabling/enabling interrupts during the runtime is needed for example for re-entrancy reasons, then you could possibly manage this with proper interrupt grouping and priority mapping. The challenge with disabling certain interrupts at runtime might make it more complex to verify and validate that the system is operating as desired, but that depends of course on the stuff you are doing.&lt;/P&gt;&lt;P&gt;I hope this helps,&lt;/P&gt;&lt;P&gt;Erich&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;PS: You might have a read at a series about ARM Cortex interrupts:&lt;/P&gt;&lt;P&gt;&lt;A href="https://mcuoneclipse.com/2016/08/14/arm-cortex-m-interrupts-and-freertos-part-1/" target="_blank"&gt;https://mcuoneclipse.com/2016/08/14/arm-cortex-m-interrupts-and-freertos-part-1/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://mcuoneclipse.com/2016/08/20/arm-cortex-m-interrupts-and-freertos-part-2/" target="_blank"&gt;https://mcuoneclipse.com/2016/08/20/arm-cortex-m-interrupts-and-freertos-part-2/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://mcuoneclipse.com/2016/08/28/arm-cortex-m-interrupts-and-freertos-part-3/" target="_blank"&gt;https://mcuoneclipse.com/2016/08/28/arm-cortex-m-interrupts-and-freertos-part-3/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 05 Jan 2023 15:49:13 GMT</pubDate>
    <dc:creator>ErichStyger</dc:creator>
    <dc:date>2023-01-05T15:49:13Z</dc:date>
    <item>
      <title>Interrupt Priority</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Interrupt-Priority/m-p/1577923#M51192</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Here we using multiple interrupts including externa, I2C, Timers,.. During run time, some of the interrupts has been disabled and enable as per the application needs. So my doubt is, when the priority of the interrupt has to assigned. During enable of interrupt or during initialization or set all peripheral interrupts in one by one manners&lt;/P&gt;</description>
      <pubDate>Thu, 05 Jan 2023 10:46:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Interrupt-Priority/m-p/1577923#M51192</guid>
      <dc:creator>Dhaya</dc:creator>
      <dc:date>2023-01-05T10:46:56Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt Priority</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Interrupt-Priority/m-p/1578080#M51197</link>
      <description>&lt;P&gt;In principle, you can do it anytime.&lt;/P&gt;&lt;P&gt;Just keep in mind that the architecture might have some delays/caches, so you need to add memory barriers, as explained in &lt;A href="https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/" target="_blank"&gt;https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;As for myself, I initialize interrupts during the device/peripheral setup, one by one, with the global interrupts disabled. At the end, with starting the application or the RTOS, the global interrupts get enabled.&lt;/P&gt;&lt;P&gt;If disabling/enabling interrupts during the runtime is needed for example for re-entrancy reasons, then you could possibly manage this with proper interrupt grouping and priority mapping. The challenge with disabling certain interrupts at runtime might make it more complex to verify and validate that the system is operating as desired, but that depends of course on the stuff you are doing.&lt;/P&gt;&lt;P&gt;I hope this helps,&lt;/P&gt;&lt;P&gt;Erich&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;PS: You might have a read at a series about ARM Cortex interrupts:&lt;/P&gt;&lt;P&gt;&lt;A href="https://mcuoneclipse.com/2016/08/14/arm-cortex-m-interrupts-and-freertos-part-1/" target="_blank"&gt;https://mcuoneclipse.com/2016/08/14/arm-cortex-m-interrupts-and-freertos-part-1/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://mcuoneclipse.com/2016/08/20/arm-cortex-m-interrupts-and-freertos-part-2/" target="_blank"&gt;https://mcuoneclipse.com/2016/08/20/arm-cortex-m-interrupts-and-freertos-part-2/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://mcuoneclipse.com/2016/08/28/arm-cortex-m-interrupts-and-freertos-part-3/" target="_blank"&gt;https://mcuoneclipse.com/2016/08/28/arm-cortex-m-interrupts-and-freertos-part-3/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 05 Jan 2023 15:49:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Interrupt-Priority/m-p/1578080#M51197</guid>
      <dc:creator>ErichStyger</dc:creator>
      <dc:date>2023-01-05T15:49:13Z</dc:date>
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