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    <title>topic Re: lpc55sxx DFLT and PIN setting clarification in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552510#M50676</link>
    <description>&lt;P&gt;Perfect, thanks for the clarification.&lt;/P&gt;&lt;P&gt;I do have a follow-up question regarding the&amp;nbsp;CC_SOCU_PIN and&amp;nbsp;CC_SOCU_NS_PIN naming convention used in the CMPA and CFPA pages respectively.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Does the "_NS" designation used in the CFPA settings imply that the PIN/DFLT fields in the CFPA are only applicable to the Non-Secure areas, and therefore the PIN/DFLT fields in the CMPA are only applicable to the Secure areas?&lt;/P&gt;&lt;P&gt;Since the CFPA is meant to allow restrictions for Level 2 customers, does this mean that CMPA and CFPA control different parts of the MCU?&lt;/P&gt;&lt;P&gt;Or, are the fields in the&amp;nbsp;CC_SOCU_PIN and&amp;nbsp;CC_SOCU_NS_PIN controlling the same areas, and the CFPA is only giving the option to increase the restrictions as defined in the CMPA?&lt;/P&gt;</description>
    <pubDate>Fri, 11 Nov 2022 08:44:54 GMT</pubDate>
    <dc:creator>DWightman</dc:creator>
    <dc:date>2022-11-11T08:44:54Z</dc:date>
    <item>
      <title>lpc55sxx DFLT and PIN setting clarification</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552227#M50669</link>
      <description>&lt;P&gt;The AN13037 description of the DFLT / PIN configuration seems to conflict with the user manual&lt;/P&gt;&lt;P&gt;It says&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DWightman_1-1668111447711.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/199917iA506DD5F688A97AC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DWightman_1-1668111447711.png" alt="DWightman_1-1668111447711.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;and&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DWightman_2-1668111473495.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/199919i6742FD7524EFB297/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DWightman_2-1668111473495.png" alt="DWightman_2-1668111473495.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I interpret this to mean that setting the DFLT / PIN to 1/1 gives access to the specific sub-domain and that a CFPA cannot set a lower restriction level to a subdomain than what was set in the CMPA.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;However, the User Manual on page 975 says that a DFLT / PIN setting of 1 / 1 has the highest restriction level and disables access to a submodule.&amp;nbsp; I also assume that if the CMPA configures one of the submodules as 1/1, then the CFPA wouldnt be able to set it to a lower configuration.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DWightman_0-1668111398187.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/199916i991B2CBCE882789F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DWightman_0-1668111398187.png" alt="DWightman_0-1668111398187.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It would be very nice to get clarification on this.&amp;nbsp; Based on descriptions within this forum, it seems like what is described in AN13037 is wrong.&lt;/P&gt;&lt;P&gt;Also, it would be really great to understand how the CFPA can be set based on how the CMPA is set.&lt;/P&gt;</description>
      <pubDate>Thu, 10 Nov 2022 20:20:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552227#M50669</guid>
      <dc:creator>DWightman</dc:creator>
      <dc:date>2022-11-10T20:20:35Z</dc:date>
    </item>
    <item>
      <title>Re: lpc55sxx DFLT and PIN setting clarification</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552453#M50674</link>
      <description>&lt;P&gt;HI&amp;nbsp;DWightman&amp;nbsp;&lt;/P&gt;
&lt;P&gt;It's not correct. I have reported this.&lt;/P&gt;
&lt;P&gt;Please refer table in UM11126. this is correct&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ZhangJennie_0-1668151080014.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/200000i68F978EAE31E24D5/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ZhangJennie_0-1668151080014.png" alt="ZhangJennie_0-1668151080014.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;The default CC_SOCU_PIN and CC_SOCU_DFLT in PFR are all zero, and not satisfied with the inverse rule, so the ROM will open all debug permission at this condition.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ZhangJennie_1-1668151159371.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/200001iD3E2A221A9D0C5E2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ZhangJennie_1-1668151159371.png" alt="ZhangJennie_1-1668151159371.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Bellow setting disable the access.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ZhangJennie_2-1668151182427.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/200002iF40AC8ABCE79B909/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ZhangJennie_2-1668151182427.png" alt="ZhangJennie_2-1668151182427.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Hope this helps,&lt;/P&gt;
&lt;P&gt;Jun Zhang&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 11 Nov 2022 07:22:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552453#M50674</guid>
      <dc:creator>ZhangJennie</dc:creator>
      <dc:date>2022-11-11T07:22:57Z</dc:date>
    </item>
    <item>
      <title>Re: lpc55sxx DFLT and PIN setting clarification</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552510#M50676</link>
      <description>&lt;P&gt;Perfect, thanks for the clarification.&lt;/P&gt;&lt;P&gt;I do have a follow-up question regarding the&amp;nbsp;CC_SOCU_PIN and&amp;nbsp;CC_SOCU_NS_PIN naming convention used in the CMPA and CFPA pages respectively.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Does the "_NS" designation used in the CFPA settings imply that the PIN/DFLT fields in the CFPA are only applicable to the Non-Secure areas, and therefore the PIN/DFLT fields in the CMPA are only applicable to the Secure areas?&lt;/P&gt;&lt;P&gt;Since the CFPA is meant to allow restrictions for Level 2 customers, does this mean that CMPA and CFPA control different parts of the MCU?&lt;/P&gt;&lt;P&gt;Or, are the fields in the&amp;nbsp;CC_SOCU_PIN and&amp;nbsp;CC_SOCU_NS_PIN controlling the same areas, and the CFPA is only giving the option to increase the restrictions as defined in the CMPA?&lt;/P&gt;</description>
      <pubDate>Fri, 11 Nov 2022 08:44:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552510#M50676</guid>
      <dc:creator>DWightman</dc:creator>
      <dc:date>2022-11-11T08:44:54Z</dc:date>
    </item>
    <item>
      <title>Re: lpc55sxx DFLT and PIN setting clarification</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552515#M50677</link>
      <description>&lt;P&gt;It looks like I was looking at the wrong manual, and it was for the&amp;nbsp;LPC55S0x&amp;nbsp; (UM11424).&lt;/P&gt;&lt;P&gt;And as you say the UM for the LPC55S69 (UM11126) is showing the same as the AN.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 11 Nov 2022 08:53:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552515#M50677</guid>
      <dc:creator>DWightman</dc:creator>
      <dc:date>2022-11-11T08:53:57Z</dc:date>
    </item>
    <item>
      <title>Re: lpc55sxx DFLT and PIN setting clarification</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552527#M50678</link>
      <description>&lt;P&gt;yes, please refer UM11126. This is correct.&lt;/P&gt;
&lt;P&gt;For other manual problem, I have reported it.&lt;/P&gt;</description>
      <pubDate>Fri, 11 Nov 2022 09:14:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc55sxx-DFLT-and-PIN-setting-clarification/m-p/1552527#M50678</guid>
      <dc:creator>ZhangJennie</dc:creator>
      <dc:date>2022-11-11T09:14:42Z</dc:date>
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