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    <title>LPC Microcontrollersのトピック4-bit Planar EL display timing restrictions</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/4-bit-Planar-EL-display-timing-restrictions/m-p/522416#M5052</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by adampmtnw on Mon Jun 25 16:24:32 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I am working on a demo to start incorporating the LPC1788 in one of our products. I'm using the LPC1788 and a Planar EL display. According to Planar no horizontal front or back porch is required. The 177x8x UM states on page 290 horizontal timing restrictions of a horz. back and front porch of 5 clock cycles due to DMA timing restrictions. A conflicting statement in the Vertical Sync. Pulse Width register description states "The number of horz. sync line must be small ... (program to zero) ..."&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am confused; is it possible to program the HFP and HBP to zero? I am currently unable to get anything to show on the EL display and I suspect this may be part of the issue.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Additional Info:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; - 4-bit interface&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; - 1 bit per pixel&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; - 160 x 80 resolution&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Adam&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 17:55:01 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T17:55:01Z</dc:date>
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      <title>4-bit Planar EL display timing restrictions</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/4-bit-Planar-EL-display-timing-restrictions/m-p/522416#M5052</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by adampmtnw on Mon Jun 25 16:24:32 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I am working on a demo to start incorporating the LPC1788 in one of our products. I'm using the LPC1788 and a Planar EL display. According to Planar no horizontal front or back porch is required. The 177x8x UM states on page 290 horizontal timing restrictions of a horz. back and front porch of 5 clock cycles due to DMA timing restrictions. A conflicting statement in the Vertical Sync. Pulse Width register description states "The number of horz. sync line must be small ... (program to zero) ..."&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am confused; is it possible to program the HFP and HBP to zero? I am currently unable to get anything to show on the EL display and I suspect this may be part of the issue.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Additional Info:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; - 4-bit interface&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; - 1 bit per pixel&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; - 160 x 80 resolution&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Adam&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 17:55:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/4-bit-Planar-EL-display-timing-restrictions/m-p/522416#M5052</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T17:55:01Z</dc:date>
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