LPC MicrocontrollersのトピックRe: SSP test registers

SSP test registers

lpcware — Wed, 15 Jun 2016 16:38:59 GMT

Content originally posted in LPCWare by Zoltan on Fri Jun 01 05:46:29 MST 2012
As far as I can tell, the SSP on the LPC chips is a standard ARM macrocell.
However, the NXP docs does not mention the test registers what the ARM docs describe.
They are extremely handy when you have to run the SSP as a slave.
If you expect to send some data to the master and you load it to the FIFO, then if the master prematurely aborts the transfer your FIFO will not be flushed.
There is no mechanism to actually FLUSH the FIFO, thus from that point on all frames will be off.
The test registers allow you to actually flush the transmit FIFO in such situations.

I wonder if the test registers are implemented but omitted from the NXP manuals or the test mode is not realised on the silicon at all?

Thanks.

Re: SSP test registers

lpcware — Wed, 15 Jun 2016 16:39:00 GMT

Content originally posted in LPCWare by DiligentMinds.com on Fri Aug 24 16:07:37 MST 2012
Perhaps an experiment is in order? When you try it out, please post your results for the rest of us-- along with the code (please)...

Re: SSP test registers

lpcware — Wed, 15 Jun 2016 16:39:00 GMT

Content originally posted in LPCWare by arshs on Fri Sep 28 09:42:51 MST 2012
Hi:
The SSP Test registers are indeed implemented and operational in the LPC (at least in the LPC2300) family, where I have used them for exactly that purpose: clearing the TX/RX FIFOs.

Regards,

Alex