LPC1788: configuring external SDRAM

giusloq — Thu, 01 Sep 2022 10:23:50 GMT

I'm using SDRAM ISSI IS42S32200L connected to LPC1788. I configured it with the following code in CAS=3:

#define CLK0_DELAY 7 Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_EMC); /* Setup EMC Delays */ /* Move all clock delays together */ LPC_SYSCTL->EMCDLYCTL = (CLK0_DELAY) | (CLK0_DELAY << | (CLK0_DELAY << 16 | (CLK0_DELAY << 24)); /* Setup EMC Clock Divider for divide by 2 */ /* Setup EMC clock for a divider of 2 from CPU clock. Enable EMC clock for external memory setup of DRAM. */ Chip_Clock_SetEMCClockDiv(SYSCTL_EMC_DIV2); Chip_SYSCTL_PeriphReset(SYSCTL_RESET_EMC); /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */ Chip_EMC_Init(1, 0, 0); /* Init EMC Dynamic Controller */ const IP_EMC_DYN_CONFIG_T IS42S32800D_config = { EMC_NANOSECOND(64000000 / 4096), 0x01, /* Command Delayed */ 3, /* tRP */ 7, /* tRAS */ EMC_NANOSECOND(70), /* tSREX */ EMC_CLOCK(0x01), /* tAPR */ EMC_CLOCK(0x05), /* tDAL */ EMC_NANOSECOND(12), /* tWR */ EMC_NANOSECOND(60), /* tRC */ EMC_NANOSECOND(60), /* tRFC */ EMC_NANOSECOND(70), /* tXSR */ EMC_NANOSECOND(12), /* tRRD */ EMC_CLOCK(0x02), /* tMRD */ { { EMC_ADDRESS_DYCS0, /* EA Board uses DYCS0 for SDRAM */ 3, //2, /* RAS */ /* Mode Register */ EMC_DYN_MODE_WBMODE_PROGRAMMED | EMC_DYN_MODE_OPMODE_STANDARD | EMC_DYN_MODE_CAS_3 | //EMC_DYN_MODE_CAS_2 EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL | EMC_DYN_MODE_BURST_LEN_4, /* DynConfig */ EMC_DYN_CONFIG_DATA_BUS_32 | EMC_DYN_CONFIG_LPSDRAM | EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS | //EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS | EMC_DYN_CONFIG_MD_SDRAM }, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} } }; Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &IS42S32800D_config);

Is it correct?

It seems it is working, but I have some issues with certain boards, so I want to be sure this isn't related to SDRAM configured in a wrong way (maybe above some hardware limits).

Re: LPC1788: configuring external SDRAM

xiangjun_rong — Mon, 05 Sep 2022 08:33:58 GMT

Hi, Giuseppe,

I think the so-called CAS=3 means Programmable CAS latency, it is programmed into the MODE REGISTER of SDRAM. The parameter is defined in the

MC_DYN_MODE_CAS_3

MC_DYN_MODE_CAS_2

Hope it can help you

XiangJun Rong

LPC MicrocontrollersのトピックLPC1788: configuring external SDRAM

LPC1788: configuring external SDRAM

Re: LPC1788: configuring external SDRAM