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    <title>topic Re: LPC54102 power rail leakage? in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1506037#M49844</link>
    <description>&lt;P&gt;Hi&amp;nbsp;StephenYeh&amp;nbsp;&lt;/P&gt;
&lt;P&gt;This issue is linked with a internal ticket. I will keep you informed if any update.&lt;/P&gt;
&lt;P&gt;For now, I suggest you setting VDDA equal to VDD.&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Jun Zhang&lt;/P&gt;</description>
    <pubDate>Mon, 15 Aug 2022 07:19:04 GMT</pubDate>
    <dc:creator>ZhangJennie</dc:creator>
    <dc:date>2022-08-15T07:19:04Z</dc:date>
    <item>
      <title>LPC54102 power rail leakage?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1503335#M49807</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Is it possible that power rail design&lt;/P&gt;&lt;P&gt;@&amp;nbsp;VDDA:3.3V / VDD:1.8V / VREFN: 0V / VREFP:2.5V ?&lt;/P&gt;&lt;P&gt;We got the issue that VDD will leakage to 2.3V.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="StephenYeh_0-1660053260817.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/189672i488B230687229EA8/image-size/medium?v=v2&amp;amp;px=400" role="button" title="StephenYeh_0-1660053260817.png" alt="StephenYeh_0-1660053260817.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 09 Aug 2022 13:55:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1503335#M49807</guid>
      <dc:creator>StephenYeh</dc:creator>
      <dc:date>2022-08-09T13:55:39Z</dc:date>
    </item>
    <item>
      <title>Re: LPC54102 power rail leakage?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1503573#M49809</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I check the spec.(the leakage will from VIA design(it will refer. VDD) right?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="StephenYeh_0-1660092919193.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/189716iD7A7519F1A406841/image-size/medium?v=v2&amp;amp;px=400" role="button" title="StephenYeh_0-1660092919193.png" alt="StephenYeh_0-1660092919193.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 10 Aug 2022 00:56:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1503573#M49809</guid>
      <dc:creator>StephenYeh</dc:creator>
      <dc:date>2022-08-10T00:56:31Z</dc:date>
    </item>
    <item>
      <title>Re: LPC54102 power rail leakage?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1506037#M49844</link>
      <description>&lt;P&gt;Hi&amp;nbsp;StephenYeh&amp;nbsp;&lt;/P&gt;
&lt;P&gt;This issue is linked with a internal ticket. I will keep you informed if any update.&lt;/P&gt;
&lt;P&gt;For now, I suggest you setting VDDA equal to VDD.&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Jun Zhang&lt;/P&gt;</description>
      <pubDate>Mon, 15 Aug 2022 07:19:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1506037#M49844</guid>
      <dc:creator>ZhangJennie</dc:creator>
      <dc:date>2022-08-15T07:19:04Z</dc:date>
    </item>
    <item>
      <title>Re: LPC54102 power rail leakage?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1518955#M50090</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/181202"&gt;@StephenYeh&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In the limiting table, the analog input voltage should say VDDA instead of VDD. When the ADC is used, the signal levels&amp;nbsp;signal levels on analog input pins must not be above the level of VDDA at any time.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Hope this helps,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Jun Zhang&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2022 03:20:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-power-rail-leakage/m-p/1518955#M50090</guid>
      <dc:creator>ZhangJennie</dc:creator>
      <dc:date>2022-09-08T03:20:25Z</dc:date>
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