<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic lpc4088 with PHY dp83826 in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc4088-with-PHY-dp83826/m-p/1499198#M49741</link>
    <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I try to work with Ethernet PHY from ti dp83826. Data transfer via MDC, MDIO - ok. But init process fail here:&lt;/P&gt;&lt;P&gt;//Check Link status&lt;/P&gt;&lt;P&gt;for (tout = EMAC_PHY_RESP_TOUT;tout &amp;gt;=0; tout--) {&lt;/P&gt;&lt;P&gt;regv = EMAC_Read_PHY(EMAC_PHY_REG_BMSR) ;&lt;/P&gt;&lt;P&gt;if(regv &amp;amp; EMAC_PHY_BMSR_LINK_ESTABLISHED) {&lt;/P&gt;&lt;P&gt;/* Link is on*/&lt;/P&gt;&lt;P&gt;break;&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;if(tout == 0) {&lt;/P&gt;&lt;P&gt;//time out&lt;/P&gt;&lt;P&gt;return (-1) ;&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;Why no link? What mean this link? If skip this step router doesn't see my device.&amp;nbsp;&lt;/P&gt;&lt;P&gt;PHY work as master, Clk correct.&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 02 Aug 2022 04:11:10 GMT</pubDate>
    <dc:creator>kruftin</dc:creator>
    <dc:date>2022-08-02T04:11:10Z</dc:date>
    <item>
      <title>lpc4088 with PHY dp83826</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc4088-with-PHY-dp83826/m-p/1499198#M49741</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I try to work with Ethernet PHY from ti dp83826. Data transfer via MDC, MDIO - ok. But init process fail here:&lt;/P&gt;&lt;P&gt;//Check Link status&lt;/P&gt;&lt;P&gt;for (tout = EMAC_PHY_RESP_TOUT;tout &amp;gt;=0; tout--) {&lt;/P&gt;&lt;P&gt;regv = EMAC_Read_PHY(EMAC_PHY_REG_BMSR) ;&lt;/P&gt;&lt;P&gt;if(regv &amp;amp; EMAC_PHY_BMSR_LINK_ESTABLISHED) {&lt;/P&gt;&lt;P&gt;/* Link is on*/&lt;/P&gt;&lt;P&gt;break;&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;if(tout == 0) {&lt;/P&gt;&lt;P&gt;//time out&lt;/P&gt;&lt;P&gt;return (-1) ;&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;Why no link? What mean this link? If skip this step router doesn't see my device.&amp;nbsp;&lt;/P&gt;&lt;P&gt;PHY work as master, Clk correct.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 02 Aug 2022 04:11:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc4088-with-PHY-dp83826/m-p/1499198#M49741</guid>
      <dc:creator>kruftin</dc:creator>
      <dc:date>2022-08-02T04:11:10Z</dc:date>
    </item>
    <item>
      <title>Re: lpc4088 with PHY dp83826</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc4088-with-PHY-dp83826/m-p/1500398#M49757</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/204487"&gt;@kruftin&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;BMSR is the Basic Mode Status Register for your PHY device, and it seems to be a specific register, you will need to check it with the manufacturer at hand. Also, it seems you are using a custom board, could you please help me confirm this?&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;I recommend you refer to our LPC407x/8x&amp;nbsp;LPCOpen software package with ethernet drivers, stack(LWIP) and examples which work well. I think&amp;nbsp;the setup&amp;nbsp;should be similar for the different PHYs. You may use the driver and stack:&amp;nbsp;&lt;A href="https://www.nxp.com/design/microcontrollers-developer-resources/lpcopen-libraries-and-examples/lpcopen-software-development-platform-lpc40xx:LPCOPEN-SOFTWARE-FOR-LPC40XX" target="_blank"&gt;LPCOpen Software for LPC40XX | NXP Semiconductors&lt;/A&gt;.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Here are also some community posts you might find useful in your application:&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://community.nxp.com/t5/LPC-Microcontrollers/LPC4088-Ethernet-Error/m-p/550553" target="_blank"&gt;LPC4088 Ethernet Error - NXP Community&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://community.nxp.com/t5/LPC-Microcontrollers/MII-MDIO-clocking-and-control/td-p/577174" target="_blank"&gt;MII-MDIO clocking and control - NXP Community&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards, Julian&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 03 Aug 2022 17:01:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc4088-with-PHY-dp83826/m-p/1500398#M49757</guid>
      <dc:creator>Julián_AragónM</dc:creator>
      <dc:date>2022-08-03T17:01:31Z</dc:date>
    </item>
    <item>
      <title>Re: lpc4088 with PHY dp83826</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc4088-with-PHY-dp83826/m-p/1500768#M49761</link>
      <description>&lt;P&gt;Ok, thank you for advice. I suppose that problem in my custom board.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 04 Aug 2022 05:25:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc4088-with-PHY-dp83826/m-p/1500768#M49761</guid>
      <dc:creator>kruftin</dc:creator>
      <dc:date>2022-08-04T05:25:35Z</dc:date>
    </item>
  </channel>
</rss>

