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    <title>LPC Microcontrollers中的主题 about LPC17xx emac Overrun error</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/about-LPC17xx-emac-Overrun-error/m-p/522317#M4953</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by ml1234 on Sat Feb 23 02:10:32 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;1.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC17xx User manual Rev.2 Page 190, about this bit:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The data flow on the receiver data interface stalls, corrupting the packet. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;In this case the overrun bit in the status word is set and the RxError bit in the IntStatus register is set. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;This error is nonfatal.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;what reason can have this bit set?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;2.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The flow of reception statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;This error will corrupt the hardware state and requires the hardware to be soft reset. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The error is detected and sets the Overrun bit in the IntStatus register.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;how to reset the hardware?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;thx!&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2013-2-23&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 17:55:13 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T17:55:13Z</dc:date>
    <item>
      <title>about LPC17xx emac Overrun error</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/about-LPC17xx-emac-Overrun-error/m-p/522317#M4953</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by ml1234 on Sat Feb 23 02:10:32 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;1.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC17xx User manual Rev.2 Page 190, about this bit:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The data flow on the receiver data interface stalls, corrupting the packet. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;In this case the overrun bit in the status word is set and the RxError bit in the IntStatus register is set. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;This error is nonfatal.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;what reason can have this bit set?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;2.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The flow of reception statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;This error will corrupt the hardware state and requires the hardware to be soft reset. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The error is detected and sets the Overrun bit in the IntStatus register.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;how to reset the hardware?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;thx!&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2013-2-23&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 17:55:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/about-LPC17xx-emac-Overrun-error/m-p/522317#M4953</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T17:55:13Z</dc:date>
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