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    <title>LPC MicrocontrollersのトピックRe: No coprocessor UsageFault</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/No-coprocessor-UsageFault/m-p/1486551#M49522</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;As you know that the LPC4088 uses Cortex-M4 core, the register ACTLR is located at 0xE000E008 address.&lt;/P&gt;
&lt;P&gt;0xE000E008 ACTLR RW Privileged 0x00000000 Auxiliary Control Register&lt;/P&gt;
&lt;P&gt;The CPACR is located at address 0xE000ED88.&lt;/P&gt;
&lt;P&gt;0xE000ED88 CPACR RW 0x00000000 Coprocessor Access Control Register&lt;/P&gt;
&lt;P&gt;The bit 2 in ACTLR register is DISDEFWBUF, which is explained as&lt;/P&gt;
&lt;P&gt;"When set to 1, disables write buffer use during default memory map accesses. This causes all&lt;BR /&gt;BusFaults to be precise BusFaults but decreases performance because any store to memory must&lt;BR /&gt;complete before the processor can execute the next instruction.&lt;BR /&gt;Note&lt;BR /&gt;This bit only affects write buffers implemented in the Cortex-M4 processor.&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;Because this is ARM peripheral register, I suggest you contact ARM support.&lt;/P&gt;
&lt;P&gt;You can download "Cortex-M4 generic user guide" from the link:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://developer.arm.com/documentation/dui0553/latest/" target="_blank"&gt;https://developer.arm.com/documentation/dui0553/latest/&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;hope it can help you&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;XiangJun Rong&lt;/P&gt;</description>
    <pubDate>Fri, 08 Jul 2022 04:09:46 GMT</pubDate>
    <dc:creator>xiangjun_rong</dc:creator>
    <dc:date>2022-07-08T04:09:46Z</dc:date>
    <item>
      <title>No coprocessor UsageFault</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/No-coprocessor-UsageFault/m-p/1486416#M49520</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am running a code on a LPC4088 board. In part of this code, when I want to initialize the ABI protocol, the IDE gave a hard fault error. Looking into a suggestion provided here&amp;nbsp;&lt;A href="http://chmorgan.blogspot.com/2013/06/debugging-imprecise-bus-access-fault-on.html," target="_blank"&gt;http://chmorgan.blogspot.com/2013/06/debugging-imprecise-bus-access-fault-on.html,&lt;/A&gt;&amp;nbsp;I added "*(uint8_t *)0xE000E008 |= (1&amp;lt;&amp;lt;1);" to main(). Now, what I get as the error is NOCP: No coprocessor Usagefault. The processor does not support coprocessor instructions.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any ideas on how to solve this is greatly appreciated.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Note: based on this document&amp;nbsp;&lt;A href="https://web.eecs.umich.edu/~prabal/teaching/eecs373-f10/readings/ARMv7-M_ARM.pdf," target="_blank"&gt;https://web.eecs.umich.edu/~prabal/teaching/eecs373-f10/readings/ARMv7-M_ARM.pdf,&lt;/A&gt;&amp;nbsp;I tried to monitor CPACR register, this is the value in memory starting from 0xE000ED88:&amp;nbsp;00F00000 00000000 00000800 00000000 00000000.&lt;/P&gt;</description>
      <pubDate>Thu, 07 Jul 2022 21:14:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/No-coprocessor-UsageFault/m-p/1486416#M49520</guid>
      <dc:creator>bamdadslr</dc:creator>
      <dc:date>2022-07-07T21:14:28Z</dc:date>
    </item>
    <item>
      <title>Re: No coprocessor UsageFault</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/No-coprocessor-UsageFault/m-p/1486551#M49522</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;As you know that the LPC4088 uses Cortex-M4 core, the register ACTLR is located at 0xE000E008 address.&lt;/P&gt;
&lt;P&gt;0xE000E008 ACTLR RW Privileged 0x00000000 Auxiliary Control Register&lt;/P&gt;
&lt;P&gt;The CPACR is located at address 0xE000ED88.&lt;/P&gt;
&lt;P&gt;0xE000ED88 CPACR RW 0x00000000 Coprocessor Access Control Register&lt;/P&gt;
&lt;P&gt;The bit 2 in ACTLR register is DISDEFWBUF, which is explained as&lt;/P&gt;
&lt;P&gt;"When set to 1, disables write buffer use during default memory map accesses. This causes all&lt;BR /&gt;BusFaults to be precise BusFaults but decreases performance because any store to memory must&lt;BR /&gt;complete before the processor can execute the next instruction.&lt;BR /&gt;Note&lt;BR /&gt;This bit only affects write buffers implemented in the Cortex-M4 processor.&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;Because this is ARM peripheral register, I suggest you contact ARM support.&lt;/P&gt;
&lt;P&gt;You can download "Cortex-M4 generic user guide" from the link:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://developer.arm.com/documentation/dui0553/latest/" target="_blank"&gt;https://developer.arm.com/documentation/dui0553/latest/&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;hope it can help you&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;XiangJun Rong&lt;/P&gt;</description>
      <pubDate>Fri, 08 Jul 2022 04:09:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/No-coprocessor-UsageFault/m-p/1486551#M49522</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2022-07-08T04:09:46Z</dc:date>
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