<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: IAP Flash Programming causing Hard fault in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/IAP-Flash-Programming-causing-Hard-fault/m-p/522309#M4945</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by TheFallGuy on Thu Oct 16 14:55:46 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;There is an FAQ on debugging a hard fault.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;But given your PC, looks like you have stack corruption&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 16:38:28 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T16:38:28Z</dc:date>
    <item>
      <title>IAP Flash Programming causing Hard fault</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/IAP-Flash-Programming-causing-Hard-fault/m-p/522308#M4944</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by lonwalker on Thu Oct 16 14:06:16 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I have been chugging right along with my project and ran into a snag writing setup parameters within LPC824's Flash memory (sector 15) for my program to read on power-up. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am using using the LPCWare periph_flashiap project sample code snippets to my code:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Last sector address */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#define START_ADDR_LAST_SECTOR&amp;nbsp; 0x00003C00&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Size of each sector */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#define SECTOR_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1024&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* LAST SECTOR */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#define IAP_LAST_SECTOR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 15&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Number of bytes to be written to the last sector */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#define IAP_NUM_BYTES_TO_WRITE&amp;nbsp; 64&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Number elements in array */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#define ARRAY_ELEMENTS&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (IAP_NUM_BYTES_TO_WRITE / sizeof(uint32_t))&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Initialize the array data to be written to FLASH */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;for (i = 0; i &amp;lt; ARRAY_ELEMENTS; i++) {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;src_iap_array_data&lt;/SPAN&gt;&lt;I&gt; = 0x11223340 + i;&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;/* Read Part Identification Number*/&lt;BR /&gt;part_id = Chip_IAP_ReadPID();&lt;BR /&gt;DEBUGOUT("Part ID is: %x\r\n", part_id);&lt;BR /&gt;&lt;BR /&gt;/* Disable interrupt mode so it doesn't fire during FLASH updates */&lt;BR /&gt;__disable_irq();&lt;BR /&gt;&lt;BR /&gt;/* IAP Flash programming */&lt;BR /&gt;/* Prepare to write/erase the last sector */&lt;BR /&gt;ret_code = Chip_IAP_PreSectorForReadWrite(IAP_LAST_SECTOR, IAP_LAST_SECTOR);&lt;BR /&gt;&lt;BR /&gt;/* Error checking */&lt;BR /&gt;if (ret_code != IAP_CMD_SUCCESS) {&lt;BR /&gt;DEBUGOUT("Command failed to execute, return code is: %x\r\n", ret_code);&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;/* Erase the last sector */&lt;BR /&gt;ret_code = Chip_IAP_EraseSector(IAP_LAST_SECTOR, IAP_LAST_SECTOR);&lt;BR /&gt;&lt;BR /&gt;/* Error checking */&lt;BR /&gt;if (ret_code != IAP_CMD_SUCCESS) {&lt;BR /&gt;DEBUGOUT("Command failed to execute, return code is: %x\r\n", ret_code);&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;/* Prepare to write/erase the last sector */&lt;BR /&gt;ret_code = Chip_IAP_PreSectorForReadWrite(IAP_LAST_SECTOR, IAP_LAST_SECTOR);&lt;BR /&gt;&lt;BR /&gt;/* Error checking */&lt;BR /&gt;if (ret_code != IAP_CMD_SUCCESS) {&lt;BR /&gt;DEBUGOUT("Command failed to execute, return code is: %x\r\n", ret_code);&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;/* Write to the last sector */&lt;BR /&gt;ret_code = Chip_IAP_CopyRamToFlash(START_ADDR_LAST_SECTOR, src_iap_array_data, IAP_NUM_BYTES_TO_WRITE);&lt;BR /&gt;&lt;BR /&gt;/* Error checking */&lt;BR /&gt;if (ret_code != IAP_CMD_SUCCESS) {&lt;BR /&gt;DEBUGOUT("Command failed to execute, return code is: %x\r\n", ret_code);&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;/* Re-enable interrupt mode */&lt;BR /&gt;__enable_irq();&lt;BR /&gt;&lt;BR /&gt;----------------------&lt;BR /&gt;Everything executes fine until the Chip_IAP_EraseSector(IAP_LAST_SECTOR, IAP_LAST_SECTOR) function call; where Xpresso gets a HardFault_Handler call which ceases program execution.&lt;BR /&gt;I am just not quite sure how to debug what is causing this due to it is down inside the code embedded on the device itself.&amp;nbsp;&amp;nbsp;&amp;nbsp; I looked on LPCOpen forums and see that VECTPC register indicates a hint; my value is 0xFFFFFFFE which puts program counter clear up at the top of memory space?&lt;BR /&gt;&lt;BR /&gt;I also see that the IAP uses the top 32 locations of RAM, so I adjusted the Top of stack to 0x10001f80, still no joy.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Any help or direction to what is going on and where to go/debug- is greatly appreciated. &lt;BR /&gt;&lt;BR /&gt;Lon&lt;BR /&gt;&lt;/I&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 16:38:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/IAP-Flash-Programming-causing-Hard-fault/m-p/522308#M4944</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T16:38:28Z</dc:date>
    </item>
    <item>
      <title>Re: IAP Flash Programming causing Hard fault</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/IAP-Flash-Programming-causing-Hard-fault/m-p/522309#M4945</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by TheFallGuy on Thu Oct 16 14:55:46 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;There is an FAQ on debugging a hard fault.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;But given your PC, looks like you have stack corruption&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 16:38:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/IAP-Flash-Programming-causing-Hard-fault/m-p/522309#M4945</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T16:38:28Z</dc:date>
    </item>
    <item>
      <title>Re: IAP Flash Programming causing Hard fault</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/IAP-Flash-Programming-causing-Hard-fault/m-p/522310#M4946</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by lonwalker on Thu Oct 16 15:41:46 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks man for the speedy reply. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am working this issue hard,,,,, The sample program is working on the MAX824 board, but my application is not.&amp;nbsp;&amp;nbsp;&amp;nbsp; I am setting up the PIN Matrix of 824 and also have the following in top of C module since I am using Chip interface calls and not Board interface stuff----&amp;nbsp; (concerned that maybe the clock settings are not right):&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;const uint32_t OscRateIn = 12000000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;const uint32_t ExtRateIn = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The rest of the App does this before the IAP Calls:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;int main(void)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;inti;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;int qty;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;boolflashMemoryWrite;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;uint8_t ret_code;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;uint32_t part_id;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Generic Initialization */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; SystemCoreClockUpdate();&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Enable SysTick Timer */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; SysTick_Config(SystemCoreClock / TICKRATE_HZ);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Initialize GPIO */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_GPIO_Init(LPC_GPIO_PORT);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;//--------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; SwitchMatrix_Init();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//--------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Enable the clock to the Switch Matrix */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Pin Assign 8 bit Configuration */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* none */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;#if 1&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Pin Assign 1 bit Configuration */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_SWM-&amp;gt;PINENABLE0 = 0xfffffECFL;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;//--------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; IOCON_Init();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//--------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Enable IOCON clock */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Pin I/O Configuration */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[0]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[1]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[2]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[3]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[4]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[5]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[6]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[7]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[8]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[9]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[10]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[11]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[12]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[13]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[14]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[15]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[16]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[17]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[18]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[18]= 0x488;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[19]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[20]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[21]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[22]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[23]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[24]= 0x88;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[25]= 0x88;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[26]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[27]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_IOCON-&amp;gt;PIO0[28]= 0x90;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;//--------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; //&amp;nbsp;&amp;nbsp;&amp;nbsp; InputMux_Init();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; //--------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_INMUX-&amp;gt;SCT0_INMUX[0] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_INMUX-&amp;gt;SCT0_INMUX[1] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_INMUX-&amp;gt;SCT0_INMUX[2] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_INMUX-&amp;gt;SCT0_INMUX[3] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[0] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[1] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[2] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[3] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[4] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[5] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[6] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[7] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[8] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[9] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[10] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[11] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[12] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[13] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[14] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[15] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[16] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_DMATRIGMUX-&amp;gt;DMA_ITRIG_INMUX[17] = 15;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_INMUX-&amp;gt;DMA_INMUX_INMUX[0] = 31;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_INMUX-&amp;gt;DMA_INMUX_INMUX[1] = 31;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;#endif&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Make sure fixed pin function is disabled and assign something safe to it */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_SWM_DisableFixedPin(SWM_FIXED_ADC6);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_SWM_DisableFixedPin(SWM_FIXED_ADC7);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_SWM_DisableFixedPin(SWM_FIXED_ADC8);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_SWM_DisableFixedPin(SWM_FIXED_ADC9);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_IOCON_PinSetMode(LPC_IOCON, IOCON_PIO19, PIN_MODE_PULLUP);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_IOCON_PinSetMode(LPC_IOCON, IOCON_PIO20, PIN_MODE_PULLUP);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_IOCON_PinDisableOpenDrainMode(LPC_IOCON, IOCON_PIO18);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Switches&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, 0, PORTPIN_SW1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, 0, PORTPIN_SW2);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Set LEDs&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, PORTPIN_LED1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, PORTPIN_LED2);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;// PIN 17&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_IOCON_PinSetMode(LPC_IOCON, IOCON_PIO17, PIN_MODE_PULLDN);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_IOCON_PinSetMode(LPC_IOCON, IOCON_PIO17, PIN_MODE_INACTIVE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, 0, PORTPIN_MODESENSE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;// PIN 18&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_IOCON_PinSetMode(LPC_IOCON, IOCON_PIO18, PIN_MODE_INACTIVE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, 0, PORTPIN_SYNCDRIVE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, PORTPIN_SYNCDRIVE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;SYNC_STROBE_INIT();&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LED_1(OFF);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LED_2(OFF);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;mrt_counter = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;PatternNdx = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;BlinkTimePtr = PatternList[SyncMode][FlashMode][PatternNdx];&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;BlinkTimeNdx = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;SyncStrobe = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Sw1PinTime = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Sw2PinTime = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Enable SysTick Timer */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;SysTick_Config(SystemCoreClock / TICKRATE_HZ);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;This is my first NXP and ARM processor hardware design.... Its been a challenge coming up to 'speed' with everything&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I Will look for that FAQ.&amp;nbsp;&amp;nbsp;&amp;nbsp; Again TheFallGuy- Thanks&amp;nbsp; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 16:38:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/IAP-Flash-Programming-causing-Hard-fault/m-p/522310#M4946</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T16:38:29Z</dc:date>
    </item>
  </channel>
</rss>

