LPC MicrocontrollersのトピックRe: I2S channel swapping

I2S channel swapping

rsk2 — Fri, 27 May 2022 16:12:24 GMT

We are using 4 LPC5526 FlexComm modules with shared clocks to handle 4 bidirectional audio channels. We have found that the DMA flips left and right channels intermittently. Has anyone seen this problem before?

We are wondering if we should try using the SCT module to hardware trigger the DMAs using the shared WS signal.

Re: I2S channel swapping

xiangjun_rong — Tue, 31 May 2022 06:21:38 GMT

Hi,

For LPC552x, you use the I2S in master mode, both the left and right channels use the same FIFO FIFOWR, so you can not identify or control which channel you will write.

There is a flag in I2S status register, which can reflect the current channel, but the flag is only used in debugger instead of driver.

Hope it can help you

XiangJun Rong

Re: I2S channel swapping

rsk2 — Tue, 31 May 2022 16:47:25 GMT

Thanks for your help. We need to run I2S in slave mode as the LRCLK (WS) and SCLK are synchronized to the external digital audio signals. It seems like we can get this running on the right channels for hours, but then it will intermittently flip the channels. Any other ideas?

Re: I2S channel swapping

xiangjun_rong — Wed, 01 Jun 2022 06:42:38 GMT

Hi,

Regarding your question that "it will intermittently flip the channels", I have not good idea. If you have found out that the left/right channels are swapped, you can delete a sample or add a sample to correct the swap.

Hope it can help you

XiangJun Rong

Re: I2S channel swapping

rsk2 — Wed, 01 Jun 2022 18:58:49 GMT

We can not detect when the error occurs. We see that the data is in the correct channel when loaded into the buffer before the DMA transfers the ping or pong buffer to the peripheral. We do not understand what is causing the problem from there.

Re: I2S channel swapping

xiangjun_rong — Thu, 02 Jun 2022 03:01:18 GMT

Hi.

I think it is complicated why the left/right channels are swapped, for example, the FIFO overflowing or under-flowing all can lead to the channel swap. you can set the PAUSEDATA bit in CFG1 register, then poll the PAUSEDATA bit in status register, then clear the PAUSEDATA bit in CFG1 register to correct the swap.

Hope it can help you

XiangJun Rong