LPC Microcontrollers中的主题 Re: LPC 546 USART CONFIG USING REGISTER

LPC 546 USART CONFIG USING REGISTER

k_sunilgupta — Thu, 19 May 2022 07:57:00 GMT

Hi all,

i want to do register level programing using LPC546 to interface usart, anyone could help me.

This is my configuration for usart0 in LPC546 for polling mode:-

USART0->CFG |= (1UL << 0); // USART ENABLE
USART0->BRG = 115200U; // SET BAUDRATE
USART0->CFG = 0x0U; // NO PARITY
USART0->CFG &=~ (1UL << 6); // 1 STOP BIT
USART0->CFG = 0x1U; // 8 BIT DATA LENGTH

USART0->CFG &=~ (1UL << 11); // ASYNC MODE
USART0->CFG &=~ (1UL << 12); // FALLING EDGE*/

But its not working, please suggest id anyone known this thing.

Re: LPC 546 USART CONFIG USING REGISTER

frank_m — Thu, 19 May 2022 09:31:03 GMT

> i want to do register level programing using LPC546 to interface usart, anyone could help me.

Which is fine. But don't use magic numbers.

This forces others to read your code and the MCU manual in parallel, and crosscheck all your registers, bits, and shifts.

Many posters her like me are volunteers, and neither have the time nor the desire to do that.

Instead use the defines that come with the MCU-specific header in the SDK. For example, in LPC54628.h. That makes reading much easier.

Re: LPC 546 USART CONFIG USING REGISTER

k_sunilgupta — Thu, 19 May 2022 11:59:26 GMT

i have checked all bits but not finding error from my side,

Re: LPC 546 USART CONFIG USING REGISTER

frank_m — Thu, 19 May 2022 12:47:29 GMT

Did you think of enabling power and clock for the USART peripheral block ?

Re: LPC 546 USART CONFIG USING REGISTER

k_sunilgupta — Fri, 27 May 2022 10:39:00 GMT

I have POWER ON

SYSCON->PDRUNCFG[0] |= (1 << 4)

AND I did not find clock for USART pheripheral block in user mannual, Please help me to creak this

Re: LPC 546 USART CONFIG USING REGISTER

ZhangJennie — Mon, 30 May 2022 03:41:30 GMT

If your USART is from FlexComm0, you need to make sure there is clock attaching to FlexComm0.

Please check USART demo code, CLOCK_AttachClk

Re: LPC 546 USART CONFIG USING REGISTER

k_sunilgupta — Mon, 30 May 2022 05:09:27 GMT

SYSCON->AHBCLKCTRL[1] |= (1UL << 11); // FLEXCOMM0 CLOCK ENABLE
SYSCON->FCLKSEL[0] = 0x4U;
SYSCON->FRGCTRL = 0x01;

void USART_0_INIT(void)
{

USART0->CFG |= (1 << 0); // USART ENABLE
USART0->BRG = 0x67; // SET BAUD RATE
USART0->CFG &=~ (1 << 6); // 1 STOP BIT
USART0->CFG |= (1 << 2); // 8 BIT MODE
USART0->FIFOCFG |= (1 << 16) | (1 << 0); // ENABLE TX
USART0->FIFOCFG |= (1 << 17) | (1 << 1); // ENABLE RX
USART0->CFG &=~ (1 << 11); // ASYNC MODE
USART0->CFG &=~ (1 << 12); // FALLING EDGE

}

Re: LPC 546 USART CONFIG USING REGISTER

k_sunilgupta — Mon, 30 May 2022 05:10:05 GMT

please check the code i have done the needful

Re: LPC 546 USART CONFIG USING REGISTER

ZhangJennie — Mon, 30 May 2022 07:36:22 GMT

Suggest you testing usart_polling SDK demo as a standard on the board. thus we can know if HW environment is ok.

If demo code works but your code can't, make register comparison of demo and your code in debug code.

Re: LPC 546 USART CONFIG USING REGISTER

k_sunilgupta — Wed, 01 Jun 2022 07:45:39 GMT

have you ever config USART on register level programing ?

@ZhangJennie

Re: LPC 546 USART CONFIG USING REGISTER

frank_m — Wed, 01 Jun 2022 08:24:12 GMT

> have you ever config USART on register level programing ?

Easy solution.

Take the proposed SDK USART example, determine the sequence of initialisation steps either via static code analysis or debugging, and apply it to your code.

Re: LPC 546 USART CONFIG USING REGISTER

k_sunilgupta — Fri, 03 Jun 2022 04:39:42 GMT

please reply.

Re: LPC 546 USART CONFIG USING REGISTER

ZhangJennie — Mon, 06 Jun 2022 08:55:47 GMT

LPC546 only has SDK demo as official demo code. and I didn't test on other code.

If you don't use SDK, please follow the advice above, referring SDK usart demo, follow the usart initialization sequence and check the related register setting to config yours code.

Re: LPC 546 USART CONFIG USING REGISTER

k_sunilgupta — Tue, 07 Jun 2022 05:00:49 GMT

i have done it now its working fine on register level.