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    <title>topic Access to uninitialized SRAM considering the ROM bootloader on LPC55S69 &amp;amp; LPC54114. in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Access-to-uninitialized-SRAM-considering-the-ROM-bootloader-on/m-p/1440698#M48444</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We need access to 4 KiB unitialized SRAM on the LPC55S69 &amp;amp; LPC54114 MCUs.&lt;/P&gt;&lt;P&gt;Both of these have an integrated ROM bootloader which uses some of the SRAM.&lt;/P&gt;&lt;P&gt;The LPC5411x User Manual explains:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;4.3.2&lt;/SPAN&gt; &lt;SPAN&gt;Memory map after any reset&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The boot ROM is located in the memory region starting from the address 0x0300 0000.&lt;BR /&gt;&lt;SPAN class=""&gt;The &lt;SPAN class=""&gt;boot loader&lt;/SPAN&gt; is designed to run from this memory area, but both the ISP and IAP&lt;/SPAN&gt;&lt;BR /&gt;software use parts of the on-chip RAM. The RAM usage is described later in&lt;BR /&gt;Section 4.3.7.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;However Section 4.3.7 does not give a clue as to what part of the SRAM is being used by the ROM bootloader.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is there any information available on which part(s) of the SRAM (memory map) is truly uninitialized (not touched by the ROM bootloader)?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Mathias&lt;/P&gt;</description>
    <pubDate>Thu, 07 Apr 2022 14:39:43 GMT</pubDate>
    <dc:creator>Mathias_</dc:creator>
    <dc:date>2022-04-07T14:39:43Z</dc:date>
    <item>
      <title>Access to uninitialized SRAM considering the ROM bootloader on LPC55S69 &amp; LPC54114.</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Access-to-uninitialized-SRAM-considering-the-ROM-bootloader-on/m-p/1440698#M48444</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We need access to 4 KiB unitialized SRAM on the LPC55S69 &amp;amp; LPC54114 MCUs.&lt;/P&gt;&lt;P&gt;Both of these have an integrated ROM bootloader which uses some of the SRAM.&lt;/P&gt;&lt;P&gt;The LPC5411x User Manual explains:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;4.3.2&lt;/SPAN&gt; &lt;SPAN&gt;Memory map after any reset&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The boot ROM is located in the memory region starting from the address 0x0300 0000.&lt;BR /&gt;&lt;SPAN class=""&gt;The &lt;SPAN class=""&gt;boot loader&lt;/SPAN&gt; is designed to run from this memory area, but both the ISP and IAP&lt;/SPAN&gt;&lt;BR /&gt;software use parts of the on-chip RAM. The RAM usage is described later in&lt;BR /&gt;Section 4.3.7.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;However Section 4.3.7 does not give a clue as to what part of the SRAM is being used by the ROM bootloader.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is there any information available on which part(s) of the SRAM (memory map) is truly uninitialized (not touched by the ROM bootloader)?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Mathias&lt;/P&gt;</description>
      <pubDate>Thu, 07 Apr 2022 14:39:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Access-to-uninitialized-SRAM-considering-the-ROM-bootloader-on/m-p/1440698#M48444</guid>
      <dc:creator>Mathias_</dc:creator>
      <dc:date>2022-04-07T14:39:43Z</dc:date>
    </item>
    <item>
      <title>Re: Access to uninitialized SRAM considering the ROM bootloader on LPC55S69 &amp; LPC54114.</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Access-to-uninitialized-SRAM-considering-the-ROM-bootloader-on/m-p/1441158#M48453</link>
      <description>&lt;P&gt;&lt;STRONG&gt;For LPC55S69:&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;Below regions are reserved for bootloader use when the bootloader is running. The heap and the BSS, RW section need to be reserved for the ROM API use before calling the ROM APIs in user application (IAP scenario).&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="55S69.PNG" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/176351i49C6B25BE0E5C778/image-size/medium?v=v2&amp;amp;px=400" role="button" title="55S69.PNG" alt="55S69.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;For LPC54114:&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;Flash programming commands use the top 32 bytes of on-chip SRAM0. This corresponds to addresses 0x2000 FFE0 through 0x2000 FFFF. The maximum stack usage in the user allocated stack space is 128 bytes and grows downwards.&lt;/P&gt;</description>
      <pubDate>Fri, 08 Apr 2022 08:41:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Access-to-uninitialized-SRAM-considering-the-ROM-bootloader-on/m-p/1441158#M48453</guid>
      <dc:creator>jay_heng</dc:creator>
      <dc:date>2022-04-08T08:41:41Z</dc:date>
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