LPC Microcontrollers中的主题 Preventing buffer underrun at SPI slave

Preventing buffer underrun at SPI slave

perdrix — Wed, 23 Feb 2022 12:05:00 GMT

Assuming I have the following code at the SPI master:

if (length && (SSP0SR & TNF)) // Data to send and transmit FIFO isn’t full? { SSPODR = *sendBuffer++; length--; }

where length is the number of SPI message to send. If I understand things right the lower layer SPI code will transmit as fast as it can.

If the slave reads the first message and cannot reply before the next message from the master arrives then buffer underrun can occur. How to change the above code to avoid this problem please?

Re: Preventing buffer underrun at SPI slave

xiangjun_rong — Thu, 24 Feb 2022 01:22:34 GMT

Hi,

I have to say that there is NOT hand-shaking signal between SPI master and slave, it is possible that the master transfers data fast enough so that the spi slave has not enough time to read data from slave SPI receiver FIFO to memory, in the case, overflow event will happen, the received data maybe lost.

So you can add a delay with such instruction as on the master side.

__asm("nop");

to delay the master transfer.

Hope it can help you

XiangJun Rong

Re: Preventing buffer underrun at SPI slave

perdrix — Thu, 03 Mar 2022 09:40:15 GMT

If there are a number of messages in the Tx fifo, I cannot do that. Yes I can delay after adding each message to the fifo so that there's only ever a maximum of one message in the fifo, but that seems less than ideal as it rather defeats the purpose of having a fifo in the first place.