LPC MicrocontrollersのトピックInterfacing with SDRAM

Interfacing with SDRAM

lpcware — Wed, 15 Jun 2016 17:54:07 GMT

Content originally posted in LPCWare by MindBender on Wed Jul 15 06:09:29 MST 2015
Are the SDRAM bank select lines BA0 and BA1 always connected to LPC17xx address lines A13 and A14, regardless the SDRAM size? Of do we have to shift them down accordingly with smaller memories?
The manual (UM10470) says in chapter 9.13.19 on page 196:
[color=#00f]For example, for a chip select connected to:[/color]
[list]
[color=#00f] [*]a 32 bit wide memory device, choose a 32 bit wide address mapping.[/color]
[color=#00f] [*]a 16 bit wide memory device, choose a 16 bit wide address mapping.[/color]
[color=#00f] [*]four x 8 bit wide memory devices, choose a 32 bit wide address mapping.[/color]
[color=#00f] [*]two x 8 bit wide memory devices, choose a 16 bit wide address mapping.[/color]
[/list]
[color=#00f]The SDRAM bank select pins BA1 and BA0 are connected to address lines A14 and A13,
respectively.[/color]

It is unclear to me if the remark on BA0 and BA1 on the last line still belongs to the example above, or that they always need to be connected like that.

Re: Interfacing with SDRAM

lpcware — Wed, 15 Jun 2016 17:54:08 GMT

Content originally posted in LPCWare by mc on Wed Jul 15 07:12:00 MST 2015
Hi MindBender,
Yes BA1 and BA0 will be connected to A14 and A13.

Re: Interfacing with SDRAM

lpcware — Wed, 15 Jun 2016 17:54:08 GMT

Content originally posted in LPCWare by MindBender on Wed Jul 15 08:32:14 MST 2015
Thanks! Another (perceived) mystery solved!

Re: Interfacing with SDRAM

lpcware — Wed, 15 Jun 2016 17:54:09 GMT

Content originally posted in LPCWare by MikeSimmonds on Wed Jul 15 09:07:44 MST 2015
Hi.

See these application notes on this site:

AN10771, AN10935, AN10950.

They are for different devices, but provided that you don't try to blindly apply them verbatim,
they will give an increased insight to the EMC controller in the NXP devices.

Regards, Mike.