topic Re: CAN base address align restriction in LPC55 in LPC Microcontrollers

CAN base address align restriction in LPC55

javiervallori — Mon, 18 Oct 2021 07:38:41 GMT

Hi,

I recently post a question because I had a rare RAM problem. Finally I realized that the reason of the problem came from the need to align the CAN0_RAM_BASE_ADDRESS to 0x10000.

The CAN0_RAM_BASE_ADDRESS is linked into the .bss section. By default in the linker_file.ld automate generated by the MCUxpresso, the .bss output section comes after the .data output section, and both are linked into the RAM_0_1_2 (0x20000000). This RAM has a lenght of 0x10000.

So, if .data is not empty, CAN0_RAM_BASE_ADDRESS can not be linked into the address 0x20000000 because it is already use by .data vars, and the following address aligned to 0x10000, is 0x20010000, and unfortunetly is out of range of the RAM_0_1_2.

This restricion make quiet unuseful the CAN module using CAN_MSG_RAM_BASE, because any static var initialization will cause a compilation error due to RAM out of range fail.

I found a workaround, using a manual .ld file and puting the .data after the .bss, but I don't like pretty much.

In my opinion this CAN module has a very big restriction with the alignment and the range memory of this microcontroler, and is something that should be take in consideration in following developments.

This post is just to help someone that have had the same problem, and to open a discousion about it findig a better solution.

Re: CAN base address align restriction in LPC55

ZhangJennie — Fri, 05 Nov 2021 14:36:02 GMT

This problem will be fixed in SDK 2.11.0 Major Release.

Thank you for bringing the problem to our attention!

Best Regards

Jun Zhang

Re: CAN base address align restriction in LPC55

ValentinCh — Fri, 21 Jan 2022 19:42:43 GMT

Hi,

I'm facing the same issue.
I've downloaded the 2.11 SDK and the bug does not seem to have been fixed.
(I need to put the bss section before the data section)

Do you have any updates ?

Re: CAN base address align restriction in LPC55

javiervallori — Mon, 24 Jan 2022 07:07:37 GMT

Hi Valentin,

I get an alternative workaround from NXP, maybe more simple because it is just a small code change in the peripheral.c file. They propouse to add a forced CAN_MESSAGE_RAM initialization avoiding to put it in the .bss.

SDK_ALIGN(uint32_t CAN0_RAM_BASE_ADDRESS[CAN0_MESSAGE_RAM_SIZE], CAN0_BASE_ADDRESS_ALIGN_SIZE) = {1};

I hope it helps.

Re: CAN base address align restriction in LPC55

ValentinCh — Mon, 24 Jan 2022 08:44:54 GMT

I will go with it ! I didn't think about this workaround.

Thank you !

Re: CAN base address align restriction in LPC55

SynBilly — Fri, 19 Aug 2022 21:16:13 GMT

SDK_ALIGN(uint32_t CAN0_RAM_BASE_ADDRESS[CAN0_MESSAGE_RAM_SIZE], CAN0_BASE_ADDRESS_ALIGN_SIZE) = {1};

This is a working solution.

I'm not that familiar with the CONFIG TOOL yet, but will this manually inserted change (in peripheral.c) be overwritten every time I click "re-generate/update code" in CONFIG TOOL?

Or is there any workaround, so that the CONFIG TOOL does not overwrite the manually inserted change?