topic Re: LPC55s69 run on SRAM in LPC Microcontrollers

LPC55s69 run on SRAM

superliyou — Sat, 04 Sep 2021 05:28:12 GMT

dear NXP,

I use the LPC55s69 development secure project.

I can run the secure demo whitch the code is in flash. the scat file just like below:

#define m_interrupts_start 0x10000000
#define m_interrupts_size 0x00000200

#define m_text_start 0x10000200
#define m_text_size 0x0000FC00

#define m_veneer_table_start 0x1000FE00
#define m_veneer_table_size 0x200

#define m_data_start 0x30010000
#define m_data_size 0x00008000

but if I change to SRAM0 just like bellow, it can not run.

#define m_interrupts_start 0x30000000
#define m_interrupts_size 0x00000200

#define m_text_start 0x30000200
#define m_text_size 0x0000FC00

#define m_data_start 0x30010000
#define m_data_size 0x00008000

#define m_veneer_table_start 0x3000FE00
#define m_veneer_table_size 0x200

aflter load .elf, I can use the cmd "PC = 0x30004040" ,set pc

but when run to "PUSH {r7,lr}", whitch is the first instructions in “SystemInit” .it make a hardfault, I can see the "SCB--CFSR" is 0x0010, that's is a stack overflow.

Can't core0 run in SRAM0~4? It only can run in flash/Rom/SramX？

what about the Core1 ?

Re: LPC55s69 run on SRAM

xiangjun_rong — Mon, 06 Sep 2021 03:00:20 GMT

Hi, LiYou

Pls refer to the following Fig in Chapter 1 in UM11126.pdf, the Flash/ROM/SRAMX are connected to code bus directly, so core can execute code saved in Flash/ROM/SRAMX directly.

If you want to execute code in SRAM0, SRAM1,SRAM2, SRAM3, I suppose it is okay, but you have to configure the MPU module.

You can refer to the AN12423.pdf on how to set up MPU.

https://www.nxp.com.cn/docs/en/application-note/AN12423.pdf

Hope it can help you

Re: LPC55s69 run on SRAM

frank_m — Mon, 06 Sep 2021 07:52:30 GMT

> If you want to execute code in SRAM0, SRAM1,SRAM2, SRAM3, I suppose it is okay, but you have to configure the MPU module.

I suppose the X flag must be set than, to allow code execution from the MPU section.

I did not use it myself, the MPU only serves to separate "safe" and "non-safe" data in my company's applications (running on Cortex M3/M4 MCUs).

Anyway, I don't see a specific advantage of executing code from RAM - except for IAP access to the application Flash bank. The code must be loaded from Flash anyway, and both Flash and RAM are internal, so no security issue.

Or am I wrong here ?

Re: LPC55s69 run on SRAM

superliyou — Mon, 06 Sep 2021 09:14:00 GMT

So Core1 can run on SRAM without any other set because there is no MPU ?

Re: LPC55s69 run on SRAM

xiangjun_rong — Mon, 06 Sep 2021 09:19:14 GMT

Hi, Frank,

How are you!

As the screenshot, the XN bit determines if you enable a space to be instruction fetch enabled or disabled.

Because I have not the Cortex-CM33 user guide, I attach the Cortex-M4 user guide.

XiangJun Rong

Re: LPC55s69 run on SRAM

frank_m — Mon, 06 Sep 2021 10:07:16 GMT

I just assume the M33 is similar to the M3/M4 in this regard, the MPU unit (periphery/coprocessor IP) being perhaps the same. I have no experience with M33 devices myself, though.

The only time I used RAM execution was for a bootloader I wrote, to update the main Flash. And this BL did not use the MPU.

Since it is quite an extra effort, an additional source of errors, and reduces the available RAM for data usage, the benefits should outweight the drawbacks. And it rarely does.

Re: LPC55s69 run on SRAM

superliyou — Tue, 07 Sep 2021 01:55:11 GMT

Thanks all of you. LPC55s69 have two cores. Core1 can run on sram without any other set. So I try to run core0 on sram.

I thought about a use case. Bootloader and two core's image are all in flash. and the image of two cores are Coding& Encrypted. when power on and reset, bootloader correction&decrypt the image and load them on SRAM.

Re: LPC55s69 run on SRAM

xiangjun_rong — Thu, 09 Sep 2021 05:53:49 GMT

Hi,

I have tried to test the code to run in SRAM0,SRAM1..., I confirm that there is not any problem to run in RAM0, RAM1,RAM2,RAM3, it is not necessary to initialize MPU.

I use the led_blinky of LPC55S69 project, and modify the code as following. The result is LED can toggle. The __RAMFUNC(RAM1) void toggle_Led(void) is put in RAM0

XiangJun Rong

#include "pin_mux.h"
#include "fsl_power.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_LED_PORT BOARD_LED_BLUE_GPIO_PORT
#define BOARD_LED_PIN BOARD_LED_BLUE_GPIO_PIN

/*******************************************************************************
* Prototypes
******************************************************************************/

/*******************************************************************************
* Variables
******************************************************************************/
volatile uint32_t g_systickCounter;

/*******************************************************************************
* Code
******************************************************************************/
void SysTick_Handler(void)
{
if (g_systickCounter != 0U)
{
g_systickCounter--;
}
}

void SysTick_DelayTicks(uint32_t n)
{
g_systickCounter = n;
while (g_systickCounter != 0U)
{
}
}
void toggle_Led(void);
/*!
* @brief Main function
*/
int main(void)
{
/* Init output LED GPIO. */
GPIO_PortInit(GPIO, BOARD_LED_PORT);
/* Board pin init */
/* set BOD VBAT level to 1.65V */
POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
BOARD_InitPins();
SystemCoreClockUpdate();

/* Set systick reload value to generate 1ms interrupt */
if (SysTick_Config(SystemCoreClock / 1000U))
{
while (1)
{
}
}

while (1)
{
/* Delay 1000 ms */
SysTick_DelayTicks(1000U);
// GPIO_PortToggle(GPIO, BOARD_LED_PORT, 1u << BOARD_LED_PIN);
toggle_Led();
}
}

__RAMFUNC(RAM1) void toggle_Led(void)
{
GPIO_PortToggle(GPIO, BOARD_LED_PORT, 1u << BOARD_LED_PIN);
}

Re: LPC55s69 run on SRAM

superliyou — Thu, 09 Sep 2021 08:45:00 GMT

Hi xiangjun,

thanks a lot!

I test the led_blinky demo project is OK. I change the scat file like below and it can also run on sram0.

#define m_interrupts_start 0x20000000
#define m_interrupts_size 0x00000200

#define m_text_start 0x20000200
#define m_text_size 0x00010000

#define m_data_start 0x20010000
#define m_data_size 0x00023000

You can try secure project demo bellow if you have time. I can't run it the same way. thanks a lot!

“trustzone_examples\secure_faults”