LPC MicrocontrollersのトピックRe: Pin behavior during power up

Pin behavior during power up

RodrigoEngComp — Mon, 16 Aug 2021 17:11:09 GMT

I'm using a LPCXpresso54018 board and at the moment I energize two pin board has the behavior shown in the attached image, even if it's a short time, it affects the project's operation.

Is there anything I could do to avoid this high state?

Thanks for yout attention, regards.

Re: Pin behavior during power up

Alice_Yang — Tue, 17 Aug 2021 03:02:13 GMT

Hello RodrigoEngComp,

How about set pin MODE to Pull-down resistor enabled, or connect a external pull-down resistor with that pin.

Alice

Re: Pin behavior during power up

RodrigoEngComp — Tue, 17 Aug 2021 12:22:25 GMT

Hey Alice,

The pin is being used as pwm, and with the following characteristics:

const uint32_t port3_pin10_config = (
IOCON_PIO_FUNC3 |
IOCON_PIO_MODE_INACT | // I tried using the MODE_PULLDOWN function
IOCON_PIO_INV_DI |
IOCON_PIO_DIGITAL_EN |
IOCON_PIO_INPFILT_OFF |
IOCON_PIO_SLEW_STANDARD |
IOCON_PIO_OPENDRAIN_DI
);
IOCON_PinMuxSet(IOCON, PORT3_IDX, PIN10_IDX, port3_pin10_config);

In this way, the output of this pin is connected to the non-inverting port of an Ampop 741.

Regards, RA.

Re: Pin behavior during power up

Alice_Yang — Thu, 19 Aug 2021 08:49:25 GMT

Hello RodrigoEngComp,

This is a know issue, you can have a look at Errata:

3.7 IOCON.1: On power-up the standard GPIO pins are not in high Z
mode by default
Introduction:
On the LPC540xx devices, on power-up, pins PIO0_0 to PIO0_31, PIO1_0 to PIO1_31,
PIO2_0 to PIO2_31, PIO3_0 to PIO3_31, PIO4_0 to PIO4_31, and PIO5_0 to PIO5_10
are in high Z mode by default (internal pull-up resistor and internal pull-down resistor are
disabled).
Problem:
Only on the LPC540xx device revision 0A (Boot ROM version 21.0), on power-up, pins
PIO0_0 to PIO0_31, PIO1_0 to PIO1_31, PIO2_0 to PIO2_31, PIO3_0 to PIO3_31,
PIO4_0 to PIO4_31, and PIO5_0 to PIO5_10 have the internal pull-ups enabled and are
not in high Z mode by default. Depending on the application, this can cause a higher
in-rush current and/or external circuits connected to the GPIO pins to work in an
unexpected manner.
Work-around:
This issue will be fixed in the next device revision 1B (Boot ROM version 21.1). Users
should carefully design their application and consider the impact of the GPIOs’ default
change from device revision 0A to device revision 1B. The user can identify the device
revisions by reading the DEVICE_ID1 register or by calling the Boot ROM version ISP/IAP
function.

Alice