Maximum Allowable Delays SPI for LPC55S69

pbguitar — Tue, 20 Jul 2021 19:43:19 GMT

I have a customer with a question regarding delays between individual lines of a SPI interface:

Regarding the Flexcomm ports. For the SPI bus to our RF transceiver of choice, do the MOSI, MISO, clk and slave select signals have to come from the same Flexcomm port, or can I route MISO on Flexcomm1, MOSI on Flexcomm2, CLK from Flexcomm3, and CS on Flexcomm4? (all split up across 4 different Flexcomms).

We are attempting to create a 4 trace routing pattern from one side of the MCU instead of splitting them around all sides of the MCU.

Do you have any insight if we might see issues running the Flexcomm in a split scenario? Would we see speed limitations for example?

Re: Maximum Allowable Delays SPI for LPC55S69

Alice_Yang — Wed, 21 Jul 2021 09:27:39 GMT

Hello pbguitar,

It seems this is the same qus

1) "Regarding the Flexcomm ports. For the SPI bus to our RF transceiver of choice, do the MOSI, MISO, clk and slave select signals have to come from the same Flexcomm port, or can I route MISO on Flexcomm1, MOSI on Flexcomm2, CLK from Flexcomm3, and CS on Flexcomm4? (all split up across 4 different Flexcomms)."
->> NO, the four signals must come from one flexcomm that you configure it as SPI.
2)"We are attempting to create a 4 trace routing pattern from one side of the MCU instead of splitting them around all sides of the MCU. Do you have any insight if we might see issues running the Flexcomm in a split scenario? Would we see speed limitations for example? "

->> Sorry I'm not very understand your this question meaning, could you please describe it more detail, thanks.

Alice

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Maximum Allowable Delays SPI for LPC55S69

Re: Maximum Allowable Delays SPI for LPC55S69