LPC MicrocontrollersのトピックRe: LPC54S018J4M spifi clock speed

LPC54S018J4M spifi clock speed

rex_lam — Mon, 26 Apr 2021 23:32:09 GMT

The example spifi source code from mcu-boot initializes the spifi clock speed to 24MHz. Is this NXP's recommendation for the spifi clock speed for spifi flash in LPC54S018J4M? I was wondering if a higher clock rate would be safe to use. Please advise.

Re: LPC54S018J4M spifi clock speed

ZhangJennie — Wed, 28 Apr 2021 06:00:47 GMT

Hi rex_lam

According to Datasheet,

Quad SPI Flash Interface with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.

Have a nice day,

Jun Zhang

Re: LPC54S018J4M spifi clock speed

rex_lam — Wed, 28 Apr 2021 14:54:33 GMT

Hi Jun,

Thank you for responding. 52MB/s data rate is not the same as the clock frequency, as it could take into account 4-bit data. Could you advise what the highest allowed clock frequency should be for spifi flash?

Rex

Re: LPC54S018J4M spifi clock speed

ZhangJennie — Thu, 29 Apr 2021 10:10:16 GMT

According to UM

Transfer rates of up to SPIFI_CLK/2 bytes per second. This is for 4bit data.

According DS,

Quad SPI Flash Interface with 1-, 2-, or 4-bit data at rates of up to 52 MB per second. the maximal 52MB is for 4bit data

So we can say maximal SPIFI_CLK is 104MHz.

Here is SPIFI clock source

If you choose internal FRO96,

for 4bit data, maximal rate is 96/2=48MB,

For 1bit data, maximal rate is 96/8=12MB

to get 52MB maximal rate, you need use external clock and configure PLL to reach 104M SPIFI_CLK.

Have a nice day,

Jun Zhang

Re: LPC54S018J4M spifi clock speed

rex_lam — Thu, 29 Apr 2021 18:56:53 GMT

Jun,

Thank you for the clarification. Looking at the XIP project examples in LPC54S018J4M's SDK, it looks like all example XIP projects specify a baud rate of 24MHz by not defining IMG_BAUDRATE.

From the UM:

From the startup file:

#ifdef IMG_BAUDRATE
.long IMG_BAUDRATE /* (0x1C) image baudrate */
#else
.long 0 /* (0x1C) reserved */
#endif

Is this indicative of some issue if the baudrate were set higher?

Also, is it possible for NXP to use a different flash part within LPC54S018J4M such that a higher baudrate might not work?

Rex

Re: LPC54S018J4M spifi clock speed

rex_lam — Thu, 06 May 2021 15:40:15 GMT

I haven't received a response to my recent questions. Does anyone know why the example XIP projects use 24MHz rather than a higher clock speed?

Re: LPC54S018J4M spifi clock speed

ZhangJennie — Mon, 10 May 2021 04:06:46 GMT

Hi,

We can refer this table for spifi clock speed setting. The default IMG_BAUDRATE is 0 which means SPIFI clock speed is 24000000. In source code, when set IMG_BAUDRATE as 96000000 or bigger, SPIFI clock speed is 96000000.

So if you want to change SPIFI clock with IMG_BAUDRATE, the maximal clock value is 96000000. The limitation is due to ROM code use internal FRO as clock source.

If you want to get higher SPIFI clock, for example 100MHz, an external clock source and PLL configuration are needed. You can configure SPIFI clock source and divider in source code to get higher SPIFI clock.

Have a nice day,

Jun Zhang