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    <title>LPC MicrocontrollersのトピックRe: 17bit or 25bit spi frame using Non blocking transfer function</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/17bit-or-25bit-spi-frame-using-Non-blocking-transfer-function/m-p/1221488#M43745</link>
    <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/125359"&gt;@iann&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Looking at the API, I saw that you're saving the configuration for the data width in the temporal structure and not directly in the register. Try writing directly to the&amp;nbsp;FIFOWR register.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Alexis Andalon&lt;/P&gt;</description>
    <pubDate>Tue, 26 Jan 2021 22:19:57 GMT</pubDate>
    <dc:creator>Alexis_A</dc:creator>
    <dc:date>2021-01-26T22:19:57Z</dc:date>
    <item>
      <title>17bit or 25bit spi frame using Non blocking transfer function</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/17bit-or-25bit-spi-frame-using-Non-blocking-transfer-function/m-p/1219730#M43713</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi All,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;A while ago I had a problem interfacing to a device using a 9 or 10 bit address word (previous thread&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;&lt;A href="https://community.nxp.com/t5/LPC-Microcontrollers/17bit-or-25bit-spi-frame-using-LPC546xx-family/m-p/1096989" target="_self"&gt;17bit or 25bit spi frame using LPC546xx family&lt;/A&gt;&amp;nbsp;) which was solved with a change to the sdk and an extra function to change the bit width which worked well when using the spi blocking functions.&lt;/SPAN&gt;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;status_t SPI_ChangeTransferWidth(SPI_Type *base, spi_data_width_t datawidth){
    uint32_t instance;
    
    instance  = SPI_GetInstance(base);
    /* store configuration */
    g_configs[instance].dataWidth = datawidth;
}&lt;/LI-CODE&gt;&lt;P&gt;However we're now moving into production code using the non blocking functions for spi and these ignore the change to the width is there a way to achieve the same?&lt;/P&gt;&lt;P&gt;Kind regards&lt;/P&gt;&lt;P&gt;Ian&lt;/P&gt;</description>
      <pubDate>Fri, 22 Jan 2021 16:29:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/17bit-or-25bit-spi-frame-using-Non-blocking-transfer-function/m-p/1219730#M43713</guid>
      <dc:creator>iann</dc:creator>
      <dc:date>2021-01-22T16:29:38Z</dc:date>
    </item>
    <item>
      <title>Re: 17bit or 25bit spi frame using Non blocking transfer function</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/17bit-or-25bit-spi-frame-using-Non-blocking-transfer-function/m-p/1221488#M43745</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/125359"&gt;@iann&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Looking at the API, I saw that you're saving the configuration for the data width in the temporal structure and not directly in the register. Try writing directly to the&amp;nbsp;FIFOWR register.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Alexis Andalon&lt;/P&gt;</description>
      <pubDate>Tue, 26 Jan 2021 22:19:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/17bit-or-25bit-spi-frame-using-Non-blocking-transfer-function/m-p/1221488#M43745</guid>
      <dc:creator>Alexis_A</dc:creator>
      <dc:date>2021-01-26T22:19:57Z</dc:date>
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