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    <title>LPC MicrocontrollersのトピックRe: Merging default RAM-Blocks results in crash</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188957#M43039</link>
    <description>&lt;P&gt;thanks&lt;/P&gt;&lt;P&gt;that did the trick. further, i was able to join RamAHB32, RamAHB16 und RamAHB_ETB16&lt;/P&gt;</description>
    <pubDate>Wed, 25 Nov 2020 12:26:28 GMT</pubDate>
    <dc:creator>jack5</dc:creator>
    <dc:date>2020-11-25T12:26:28Z</dc:date>
    <item>
      <title>Merging default RAM-Blocks results in crash</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188303#M43021</link>
      <description>&lt;P&gt;Hey&lt;/P&gt;&lt;P&gt;I am working with the LPC43S57.&lt;/P&gt;&lt;P&gt;My programm needs a lot of ram. By default there are 5 RAM-Block (RamLoc32, RamLoc40,&amp;nbsp;RamAHB32,&amp;nbsp;&amp;nbsp;RamAHB16,&amp;nbsp;&amp;nbsp;RamAHB_ETB16). The Code in question requires a little less than 50kB. For this reason i thought i could merge the RAM-Blocks RamLoc32 and RamLoc40 to create a RamLoc72 Block.&lt;/P&gt;&lt;P&gt;This does make it possible to build the project (See attachement).&lt;/P&gt;&lt;P&gt;But when trying to debug the code the programm crashes for some reason (see attachements).&lt;/P&gt;&lt;P&gt;I created a default projekt, where the main() consists of a while(1)-loop incrementing an intereger, with and without the ram-merging. I was able to run/debug the code without the ram being merged but the default projekt crashed when being debugged when the ram had been merged.&lt;/P&gt;&lt;P&gt;What part am I missing?&lt;/P&gt;&lt;P&gt;Thanks a lot.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Jack&lt;/P&gt;</description>
      <pubDate>Tue, 24 Nov 2020 15:52:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188303#M43021</guid>
      <dc:creator>jack5</dc:creator>
      <dc:date>2020-11-24T15:52:15Z</dc:date>
    </item>
    <item>
      <title>Re: Merging default RAM-Blocks results in crash</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188312#M43022</link>
      <description>&lt;P&gt;The content of the linker file:&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;* GENERATED FILE - DO NOT EDIT&lt;BR /&gt;* (c) Code Red Technologies Ltd, 2008-2013&lt;BR /&gt;* (c) NXP Semiconductors 2013-2020&lt;BR /&gt;* Generated linker script file for LPC43S57&lt;BR /&gt;* Created from linkscript.ldt by FMCreateLinkLibraries&lt;BR /&gt;* Using Freemarker v2.3.23&lt;BR /&gt;* LPCXpresso v8.2.2 [Build 650] [2016-09-09] on 24.11.2020 16:40:39&lt;BR /&gt;*/&lt;/P&gt;&lt;P&gt;INCLUDE "vogelprojekt_Debug_library.ld"&lt;BR /&gt;INCLUDE "vogelprojekt_Debug_memory.ld"&lt;/P&gt;&lt;P&gt;ENTRY(ResetISR)&lt;/P&gt;&lt;P&gt;SECTIONS&lt;BR /&gt;{&lt;BR /&gt;.text_Flash2 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;FILL(0xff)&lt;BR /&gt;*(.text_Flash2*) /* for compatibility with previous releases */&lt;BR /&gt;*(.text_MFlashB512*) /* for compatibility with previous releases */&lt;BR /&gt;*(.text.$Flash2*)&lt;BR /&gt;*(.text.$MFlashB512*)&lt;BR /&gt;*(.rodata.$Flash2*)&lt;BR /&gt;*(.rodata.$MFlashB512*)&lt;BR /&gt;} &amp;gt; MFlashB512&lt;/P&gt;&lt;P&gt;/* MAIN TEXT SECTION */&lt;BR /&gt;.text : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;FILL(0xff)&lt;BR /&gt;__vectors_start__ = ABSOLUTE(.) ;&lt;BR /&gt;KEEP(*(.isr_vector))&lt;BR /&gt;/* Global Section Table */&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;__section_table_start = .;&lt;BR /&gt;__data_section_table = .;&lt;BR /&gt;LONG(LOADADDR(.data));&lt;BR /&gt;LONG( ADDR(.data));&lt;BR /&gt;LONG( SIZEOF(.data));&lt;BR /&gt;LONG(LOADADDR(.data_RAM2));&lt;BR /&gt;LONG( ADDR(.data_RAM2));&lt;BR /&gt;LONG( SIZEOF(.data_RAM2));&lt;BR /&gt;LONG(LOADADDR(.data_RAM3));&lt;BR /&gt;LONG( ADDR(.data_RAM3));&lt;BR /&gt;LONG( SIZEOF(.data_RAM3));&lt;BR /&gt;LONG(LOADADDR(.data_RAM4));&lt;BR /&gt;LONG( ADDR(.data_RAM4));&lt;BR /&gt;LONG( SIZEOF(.data_RAM4));&lt;BR /&gt;__data_section_table_end = .;&lt;BR /&gt;__bss_section_table = .;&lt;BR /&gt;LONG( ADDR(.bss));&lt;BR /&gt;LONG( SIZEOF(.bss));&lt;BR /&gt;LONG( ADDR(.bss_RAM2));&lt;BR /&gt;LONG( SIZEOF(.bss_RAM2));&lt;BR /&gt;LONG( ADDR(.bss_RAM3));&lt;BR /&gt;LONG( SIZEOF(.bss_RAM3));&lt;BR /&gt;LONG( ADDR(.bss_RAM4));&lt;BR /&gt;LONG( SIZEOF(.bss_RAM4));&lt;BR /&gt;__bss_section_table_end = .;&lt;BR /&gt;__section_table_end = . ;&lt;BR /&gt;/* End of Global Section Table */&lt;/P&gt;&lt;P&gt;*(.after_vectors*)&lt;/P&gt;&lt;P&gt;/* Code Read Protection data */&lt;BR /&gt;. = 0x000002FC ;&lt;BR /&gt;PROVIDE(__CRP_WORD_START__ = .) ;&lt;BR /&gt;KEEP(*(.crp))&lt;BR /&gt;PROVIDE(__CRP_WORD_END__ = .) ;&lt;BR /&gt;ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");&lt;BR /&gt;/* End of Code Read Protection */&lt;BR /&gt;} &amp;gt;MFlashA512&lt;/P&gt;&lt;P&gt;.text : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;*(.text*)&lt;BR /&gt;*(.rodata .rodata.* .constdata .constdata.*)&lt;BR /&gt;. = ALIGN(4);&lt;BR /&gt;} &amp;gt; MFlashA512&lt;BR /&gt;/*&lt;BR /&gt;* for exception handling/unwind - some Newlib functions (in common&lt;BR /&gt;* with C++ and STDC++) use this.&lt;BR /&gt;*/&lt;BR /&gt;.ARM.extab : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;*(.ARM.extab* .gnu.linkonce.armextab.*)&lt;BR /&gt;} &amp;gt; MFlashA512&lt;BR /&gt;__exidx_start = .;&lt;/P&gt;&lt;P&gt;.ARM.exidx : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;*(.ARM.exidx* .gnu.linkonce.armexidx.*)&lt;BR /&gt;} &amp;gt; MFlashA512&lt;BR /&gt;__exidx_end = .;&lt;/P&gt;&lt;P&gt;_etext = .;&lt;BR /&gt;&lt;BR /&gt;/* DATA section for RamAHB32 */&lt;BR /&gt;.data_RAM2 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;FILL(0xff)&lt;BR /&gt;PROVIDE(__start_data_RAM2 = .) ;&lt;BR /&gt;*(.ramfunc.$RAM2)&lt;BR /&gt;*(.ramfunc.$RamAHB32)&lt;BR /&gt;*(.data.$RAM2*)&lt;BR /&gt;*(.data.$RamAHB32*)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;PROVIDE(__end_data_RAM2 = .) ;&lt;BR /&gt;} &amp;gt; RamAHB32 AT&amp;gt;MFlashA512&lt;/P&gt;&lt;P&gt;/* DATA section for RamAHB16 */&lt;BR /&gt;.data_RAM3 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;FILL(0xff)&lt;BR /&gt;PROVIDE(__start_data_RAM3 = .) ;&lt;BR /&gt;*(.ramfunc.$RAM3)&lt;BR /&gt;*(.ramfunc.$RamAHB16)&lt;BR /&gt;*(.data.$RAM3*)&lt;BR /&gt;*(.data.$RamAHB16*)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;PROVIDE(__end_data_RAM3 = .) ;&lt;BR /&gt;} &amp;gt; RamAHB16 AT&amp;gt;MFlashA512&lt;/P&gt;&lt;P&gt;/* DATA section for RamAHB_ETB16 */&lt;BR /&gt;.data_RAM4 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;FILL(0xff)&lt;BR /&gt;PROVIDE(__start_data_RAM4 = .) ;&lt;BR /&gt;*(.ramfunc.$RAM4)&lt;BR /&gt;*(.ramfunc.$RamAHB_ETB16)&lt;BR /&gt;*(.data.$RAM4*)&lt;BR /&gt;*(.data.$RamAHB_ETB16*)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;PROVIDE(__end_data_RAM4 = .) ;&lt;BR /&gt;} &amp;gt; RamAHB_ETB16 AT&amp;gt;MFlashA512&lt;/P&gt;&lt;P&gt;/* MAIN DATA SECTION */&lt;BR /&gt;.uninit_RESERVED : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;KEEP(*(.bss.$RESERVED*))&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;_end_uninit_RESERVED = .;&lt;BR /&gt;} &amp;gt; RamLoc72&lt;BR /&gt;/* Main DATA section (RamLoc72) */&lt;BR /&gt;.data : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;FILL(0xff)&lt;BR /&gt;_data = . ;&lt;BR /&gt;*(vtable)&lt;BR /&gt;*(.ramfunc*)&lt;BR /&gt;*(.data*)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;_edata = . ;&lt;BR /&gt;} &amp;gt; RamLoc72 AT&amp;gt;MFlashA512&lt;BR /&gt;/* BSS section for RamAHB32 */&lt;BR /&gt;.bss_RAM2 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;PROVIDE(__start_bss_RAM2 = .) ;&lt;BR /&gt;*(.bss.$RAM2*)&lt;BR /&gt;*(.bss.$RamAHB32*)&lt;BR /&gt;. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */&lt;BR /&gt;PROVIDE(__end_bss_RAM2 = .) ;&lt;BR /&gt;} &amp;gt; RamAHB32&lt;BR /&gt;/* BSS section for RamAHB16 */&lt;BR /&gt;.bss_RAM3 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;PROVIDE(__start_bss_RAM3 = .) ;&lt;BR /&gt;*(.bss.$RAM3*)&lt;BR /&gt;*(.bss.$RamAHB16*)&lt;BR /&gt;. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */&lt;BR /&gt;PROVIDE(__end_bss_RAM3 = .) ;&lt;BR /&gt;} &amp;gt; RamAHB16&lt;BR /&gt;/* BSS section for RamAHB_ETB16 */&lt;BR /&gt;.bss_RAM4 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;PROVIDE(__start_bss_RAM4 = .) ;&lt;BR /&gt;*(.bss.$RAM4*)&lt;BR /&gt;*(.bss.$RamAHB_ETB16*)&lt;BR /&gt;. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */&lt;BR /&gt;PROVIDE(__end_bss_RAM4 = .) ;&lt;BR /&gt;} &amp;gt; RamAHB_ETB16&lt;BR /&gt;/* MAIN BSS SECTION */&lt;BR /&gt;.bss : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;_bss = .;&lt;BR /&gt;*(.bss*)&lt;BR /&gt;*(COMMON)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;_ebss = .;&lt;BR /&gt;PROVIDE(end = .);&lt;BR /&gt;} &amp;gt; RamLoc72&lt;BR /&gt;/* NOINIT section for RamAHB32 */&lt;BR /&gt;.noinit_RAM2 (NOLOAD) : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;*(.noinit.$RAM2*)&lt;BR /&gt;*(.noinit.$RamAHB32*)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;} &amp;gt; RamAHB32&lt;BR /&gt;/* NOINIT section for RamAHB16 */&lt;BR /&gt;.noinit_RAM3 (NOLOAD) : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;*(.noinit.$RAM3*)&lt;BR /&gt;*(.noinit.$RamAHB16*)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;} &amp;gt; RamAHB16&lt;BR /&gt;/* NOINIT section for RamAHB_ETB16 */&lt;BR /&gt;.noinit_RAM4 (NOLOAD) : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;*(.noinit.$RAM4*)&lt;BR /&gt;*(.noinit.$RamAHB_ETB16*)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;} &amp;gt; RamAHB_ETB16&lt;BR /&gt;/* DEFAULT NOINIT SECTION */&lt;BR /&gt;.noinit (NOLOAD): ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;_noinit = .;&lt;BR /&gt;*(.noinit*)&lt;BR /&gt;. = ALIGN(4) ;&lt;BR /&gt;_end_noinit = .;&lt;BR /&gt;} &amp;gt; RamLoc72&lt;/P&gt;&lt;P&gt;PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);&lt;BR /&gt;PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc72 - 0);&lt;/P&gt;&lt;P&gt;/* ## Create checksum value (used in startup) ## */&lt;BR /&gt;PROVIDE(__valid_user_code_checksum = 0 -&lt;BR /&gt;(_vStackTop&lt;BR /&gt;+ (ResetISR + 1)&lt;BR /&gt;+ (NMI_Handler + 1)&lt;BR /&gt;+ (HardFault_Handler + 1)&lt;BR /&gt;+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */&lt;BR /&gt;+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */&lt;BR /&gt;+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */&lt;BR /&gt;) );&lt;BR /&gt;}&lt;/P&gt;</description>
      <pubDate>Tue, 24 Nov 2020 16:07:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188312#M43022</guid>
      <dc:creator>jack5</dc:creator>
      <dc:date>2020-11-24T16:07:47Z</dc:date>
    </item>
    <item>
      <title>Re: Merging default RAM-Blocks results in crash</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188356#M43023</link>
      <description>&lt;P&gt;It looks like you have merged RamLoc32 and RamLoc40 - but they are not contiguous!&lt;/P&gt;&lt;P&gt;RamLoc32 is 32k from 0x10000000 - 0x10007fff&lt;/P&gt;&lt;P&gt;RamLoc40 is 40k from 0x10080000 - 0x1008a000&lt;/P&gt;&lt;P&gt;Note RamLoc32 'ends' at 0x10008000 and RamLoc40 starts at 0x10080000 (count the zeros!)&lt;/P&gt;</description>
      <pubDate>Tue, 24 Nov 2020 17:07:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188356#M43023</guid>
      <dc:creator>converse</dc:creator>
      <dc:date>2020-11-24T17:07:28Z</dc:date>
    </item>
    <item>
      <title>Re: Merging default RAM-Blocks results in crash</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188957#M43039</link>
      <description>&lt;P&gt;thanks&lt;/P&gt;&lt;P&gt;that did the trick. further, i was able to join RamAHB32, RamAHB16 und RamAHB_ETB16&lt;/P&gt;</description>
      <pubDate>Wed, 25 Nov 2020 12:26:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Merging-default-RAM-Blocks-results-in-crash/m-p/1188957#M43039</guid>
      <dc:creator>jack5</dc:creator>
      <dc:date>2020-11-25T12:26:28Z</dc:date>
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