topic SPI Rx interrupt not generated in LPC55S28 if we disable SPI Tx interrupt in LPC Microcontrollers

SPI Rx interrupt not generated in LPC55S28 if we disable SPI Tx interrupt

rahulshah — Tue, 17 Nov 2020 09:02:39 GMT

Hello,

I am using LPC55S28 EVM board. i have 2 LPC55S28 EVM boards and i tried to run SPI master slave SPI SDK example on that.

On Baord-1, i have flashed "lpcxpresso55s28_SDK_spi_interrupt_b2b_master" SDK example code.

And on Board-2 , i have flashed "lpcxpresso55s28_SDK_spi_interrupt_b2b_slave" SDK example code.

I have connected pins as described in Readme of the SDK example code. Readme also attached with this case.

Without any change in code everything works fine , data send from master device and received at slave device. Again same received data send from slave device and received properly at master side.

But Now i want to only receive data at slave side. So if i disable Tx -interrupt at slave side then i cannot receive data in slave device.

In "spi_interrupt_b2b_slave.c" file of SDK example code , in main functoion i have disabled tx interrupt as below :

Original : SPI_EnableInterrupts(EXAMPLE_SPI_SLAVE, kSPI_RxLvlIrq | kSPI_TxLvlIrq);

Changed to : SPI_EnableInterrupts(EXAMPLE_SPI_SLAVE, kSPI_RxLvlIrq);

So after that if Master sends data over SPI , then Rx interrupt not generated at slave side and code not goes in Irq function.

I have attached SPI master-slave example code with this case.

Can anyone explain me this behavior. How i solve this issue?

Regards,

Rahul Shah

Re: SPI Rx interrupt not generated in LPC55S28 if we disable SPI Tx interrupt

Alice_Yang — Wed, 18 Nov 2020 08:07:57 GMT

Hello Rahul Shah,

ISP must send data, at the same time it can received data.

You disable slave Tx interrupt, from the SDK slave code, we can see it can't run into interrupt at start,

so won't run slave Tx funciton " SPI_WriteData(EXAMPLE_SPI_SLAVE, (uint16_t)(srcBuff[BUFFER_SIZE - txIndex]), 0);".

You can add this function in main() to test.

Regards,

Alice

Re: SPI Rx interrupt not generated in LPC55S28 if we disable SPI Tx interrupt

rahulshah — Wed, 18 Nov 2020 14:51:57 GMT

Hi Alice_Yang,
Thanks for your reply.

So my main question is if i disable tx-interrupt from "SPI_EnableInterrupts" then i am never going in ISR. is it right?
Because if i enable Tx-interrupt , then ISR calling again and again. So i want ISR only calling when slave recieves the data over SPI otherwie ISR should not call.

So how i only receive data from ISR function without enabling Tx-interrupt.

-Regards,
Rahul Shah

Re: SPI Rx interrupt not generated in LPC55S28 if we disable SPI Tx interrupt

Alice_Yang — Thu, 19 Nov 2020 02:24:08 GMT

Hello,

So my main question is if i disable tx-interrupt from "SPI_EnableInterrupts" then i am never going in ISR. is it right?

->> No.

So how i only receive data from ISR function without enabling Tx-interrupt.

->>You can disable Tx-interrupt, while you need send data to master, at the same time, slave can received data automatically.

And if you just want to SPI slave receive, not send, you can try to the function of ignore transmit data :

(UM11126, P673)

Please also pay attention:

"To set-up a slave SPI for receive only, the control bit settings must be pushed into the
write FIFO to become active. Therefore, at least one write to the FIFOWR data bits must
be done to make the control bits active"

Regard,

Alice

Re: SPI Rx interrupt not generated in LPC55S28 if we disable SPI Tx interrupt

rahulshah — Fri, 18 Dec 2020 10:54:55 GMT

Hi ,

I have added TXIGNORE=1 as follows (1<<23):

EXAMPLE_SPI_SLAVE->FIFOWR= (0x01|
((uint32_t)SPI_FIFOWR_LEN(kSPI_Data8Bits) |
(SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(0)))) | (1 << 23)) ;

Also i have disabled tx-interrupt and disabled data sending from slave side from ISR as follows :

// if ((SPI_GetStatusFlags(EXAMPLE_SPI_SLAVE) & kSPI_TxNotFullFlag) && (txIndex > 0U))
// {
// SPI_WriteData(EXAMPLE_SPI_SLAVE, (uint16_t)(srcBuff[BUFFER_SIZE - txIndex]), 0);
// txIndex--;
// }

After that i am not getting data properly from master:

Master sends : [0,1,2,3,4,5,6,7,8,9,10,11,12,13..........63]

Slave receives : [0,0,0,0,1,0,0,0,2,0,0,0,3,0,0,1....]

If i enable data sending from slave from ISR , then everything works fine.

I have added FIFOWR logic in init function so is that TXIGNORE bit set (1<<23) in FIFOWR is ok?

Regards,

Rahul Shah