topic Re: LPC1788 and NAND flash in LPC Microcontrollers

LPC1788 and NAND flash

lpcware — Wed, 15 Jun 2016 17:47:57 GMT

Content originally posted in LPCWare by Herrbert on Wed Mar 25 08:07:54 MST 2015
Hi,

I currently have to decide if I want to go for a microSD, eMMC or bare NAND flash.

While microSD and eMMC is no problem, I can't really find information on interfacing the NAND Flash with the EMC of the LPC1788.

So here is the question: Is the EMC of the LPC1788 NAND flash (ONFI standard) compatible?

Thanks!

Re: LPC1788 and NAND flash

lpcware — Wed, 15 Jun 2016 17:47:58 GMT

Content originally posted in LPCWare by wmues on Wed Mar 25 14:17:48 MST 2015
All EMC for static RAM is NAND compatible. You have to use Chipselect-Dont-Care NAND flashes (which are standard today).
Interfacing is easy.

But: if you want to use NAND flash as storage, you need a HUGE amount of software.
So if you have this software (running Linux on the LPC1788), you can do it.

I would go for microSD. Easy solution. EMMC is like SD, but you have to solve the problem how to program the EMMC in the circuit.
(And you need a fine pitch layout for EMMC).

regards
Wolfgang

Re: LPC1788 and NAND flash

lpcware — Wed, 15 Jun 2016 17:47:59 GMT

Content originally posted in LPCWare by Herrbert on Thu Mar 26 04:55:32 MST 2015
Thank you Wolfgang.

If I interprete the datasheet correctly:

Quote:
Static chip selects each support up to 64 MB of data. By enabling the address shift
mode, static chip select 0 can support up to 256 MB, and static chip select 1 can
support up to 128 MB (see SCS register bit 0 (Section 3.3.20)

The maximal NAND-Flash the controller can handle is 256 MB? Or does this only apply to devices with seperate data and address bus? ( I need at least 8GB of NAND Flash)

(If I go for the NAND solution I would buy the middleware to manage the NAND flash)

Re: LPC1788 and NAND flash

lpcware — Wed, 15 Jun 2016 17:47:59 GMT

Content originally posted in LPCWare by wmues on Thu Mar 26 06:03:51 MST 2015
A NAND-Flash is using
- 8 Data bits
- 1 /RD line
- 1 /WR line
- 1 Ready/Busy Line
- 1 Chip Select Line
- 2 ALE/CLE Command Lines

The ALE/CLE Command Lines will be connected to 2 address lines of the CPU. I would leave A0 and A1 open (so you can do a fast 32bit IO to read/write 4 bytes at once) and connect A2 and A3 to ALE/CLE.
So the address window into the CPU memory map is very small.

If you need at least 8 GB of NAND, please check how long the duration of the initial start up is. This can be very long, if all blocks of NAND must be read once at startup time. And remember that you must do the ECC calculation in software, which will limit the read spead. Therefore, performance will be a lot lower than EMMC/SD.

regards
Wolfgang