LPC Microcontrollers中的主题 Re: LPC55S69: enable SRAM clocks

LPC55S69: enable SRAM clocks

EugeneHiihtaja — Fri, 05 Jun 2020 10:49:37 GMT

Hi !

For worj with USB SRAM I should enable clock kCLOCK_UsbRam1 explictly in my code e.g. CLOCK_EnableClock(kCLOCK_UsbRam1). ConfigTool is also not generate this line in any mode.

But what about other SRAM /flash section and Flash ?

There are mentioned in clock_ip_t enumeration

kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),

Are the enabled by default ? Or BootROM enable those.

Or the managed by some PowerLib API or ROM api.

How to undestand ?

Regards,

Eugene

Re: LPC55S69: enable SRAM clocks

diego_charles — Mon, 08 Jun 2020 17:20:55 GMT

Hi Eugene!

I am working on your question.

Please, provide me additional time to check

Regards,

Diego.

Re: LPC55S69: enable SRAM clocks

diego_charles — Fri, 12 Jun 2020 15:37:21 GMT

Hi Eugene!

Thank you for your patience,

On the beginning of your application their controllers are already enabled by default, as we can see

on the following screenshot

Regards,

Diego

Re: LPC55S69: enable SRAM clocks

EugeneHiihtaja — Mon, 15 Jun 2020 12:02:09 GMT

Hi diego.charles‌ !

I can see in UM, default value for AHBCLKCTRL0 register is specified. It means SRAMn clocks enabled somewhere in bootrom. In this case is difficult to trust if clocks always will be enabled there ( or disabled/enabled again ) and SRAM retain over reboot in next versions of bootrom if any.

By the way, I haven't found any clock enable for SRAM X area. Is this type of SRAM always ON or it is just in other registers ?

But I think it is good idea to have clear spec. in what states registers remains after bootrom.

Regards,

Eugene

Re: LPC55S69: enable SRAM clocks

diego_charles — Mon, 06 Jul 2020 14:05:36 GMT

Hi Eugene,

You should not worry about the SRAM X areas, they are enabled by default.

As you know, you could control their retention state during low power modes using the sram_retention_ctrl register.

Regards,

Diego