LPC Microcontrollers中的主题 LPC3141, CS High to OE High Timing Question

LPC3141, CS High to OE High Timing Question

StanleyH — Tue, 26 Nov 2019 04:03:01 GMT

Hi Support team,

We have a question about the timing specification in the LPC3141 datasheet. Need some explanation.

Please refer the tCSHOEH specification in the SRAM controller module as below. The minimum requirement is 3ns. However our typical is 0ns. Seems strange. Is the data correct? If yes, can you please give some explanation. Thanks.

-Customer, Delta IABU.

Re: LPC3141, CS High to OE High Timing Question

xiangjun_rong — Wed, 27 Nov 2019 09:18:51 GMT

Hi, Stanley,

Regarding your question, I have consulted with engineer in AE team, we think it is a typo, it should be -3ns instead of 3ns.
The spec tCSHOEH is the time from CS HIGH to OE HIGH, when the rising edge of OE signal is before the rising edge of CS signal, it is a negative value. It can explain why the minimum is 3, typical is 0. In other words, it should be:
minimum typical
-3ns 0
Hope it can help you.

Re: LPC3141, CS High to OE High Timing Question

StanleyH — Sat, 30 Nov 2019 07:08:09 GMT

Hi X.J,

Thanks a lot for the reply.