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    <title>LPC MicrocontrollersのトピックCMSIS FCLKSEL10 LPC54018</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/CMSIS-FCLKSEL10-LPC54018/m-p/1018932#M39854</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi&lt;/DIV&gt;&lt;DIV&gt;In the SDK 2.7.0 for LPC54018 I have found this SYSCON_Type struct rather odd. The SPI10 with its FCLKSEL is defined separately from other SPI interface FCLKSEL. What is the reason? Can this be changed in the next SDK?&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;SDK_2.7.0_LPCXpresso54018\devices\LPC54018\LPC54018.h&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="text-decoration: underline;"&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="text-decoration: underline;"&gt;&lt;EM&gt;&lt;STRONG&gt;Status Quo&lt;/STRONG&gt;&lt;/EM&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;typedef struct {&lt;BR /&gt;&amp;nbsp; ....&lt;BR /&gt;&amp;nbsp; __IO uint32_t FCLKSEL[10];&lt;BR /&gt;&amp;nbsp; __IO uint32_t FCLKSEL10;&lt;BR /&gt;&amp;nbsp; ....&lt;BR /&gt;} SYSCON_Type;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM style="text-decoration: underline; "&gt;&lt;STRONG&gt;Proposal for change&lt;/STRONG&gt;&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;typedef struct {&lt;BR /&gt;&amp;nbsp; ....&lt;BR /&gt;&amp;nbsp; __IO uint32_t FCLKSEL[11];&lt;BR /&gt;&amp;nbsp; ....&lt;BR /&gt;} SYSCON_Type;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Many thanks&lt;/DIV&gt;&lt;DIV&gt;Dani&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 26 Mar 2020 06:13:34 GMT</pubDate>
    <dc:creator>danielgull</dc:creator>
    <dc:date>2020-03-26T06:13:34Z</dc:date>
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      <title>CMSIS FCLKSEL10 LPC54018</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/CMSIS-FCLKSEL10-LPC54018/m-p/1018932#M39854</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi&lt;/DIV&gt;&lt;DIV&gt;In the SDK 2.7.0 for LPC54018 I have found this SYSCON_Type struct rather odd. The SPI10 with its FCLKSEL is defined separately from other SPI interface FCLKSEL. What is the reason? Can this be changed in the next SDK?&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;SDK_2.7.0_LPCXpresso54018\devices\LPC54018\LPC54018.h&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="text-decoration: underline;"&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="text-decoration: underline;"&gt;&lt;EM&gt;&lt;STRONG&gt;Status Quo&lt;/STRONG&gt;&lt;/EM&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;typedef struct {&lt;BR /&gt;&amp;nbsp; ....&lt;BR /&gt;&amp;nbsp; __IO uint32_t FCLKSEL[10];&lt;BR /&gt;&amp;nbsp; __IO uint32_t FCLKSEL10;&lt;BR /&gt;&amp;nbsp; ....&lt;BR /&gt;} SYSCON_Type;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM style="text-decoration: underline; "&gt;&lt;STRONG&gt;Proposal for change&lt;/STRONG&gt;&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;typedef struct {&lt;BR /&gt;&amp;nbsp; ....&lt;BR /&gt;&amp;nbsp; __IO uint32_t FCLKSEL[11];&lt;BR /&gt;&amp;nbsp; ....&lt;BR /&gt;} SYSCON_Type;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Many thanks&lt;/DIV&gt;&lt;DIV&gt;Dani&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Mar 2020 06:13:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/CMSIS-FCLKSEL10-LPC54018/m-p/1018932#M39854</guid>
      <dc:creator>danielgull</dc:creator>
      <dc:date>2020-03-26T06:13:34Z</dc:date>
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    <item>
      <title>Re: CMSIS FCLKSEL10 LPC54018</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/CMSIS-FCLKSEL10-LPC54018/m-p/1018933#M39855</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, Daniel,&lt;/P&gt;&lt;P&gt;Thank you for your pointing out the drawback of the SYSCON_Type structure. As you know that the UM11060.pdf defines two Table:&lt;/P&gt;&lt;P&gt;Table 121. Flexcomm Interface clock source select registers (FCLKSEL0-9, main syscon: offsets 0x2B0 through&lt;BR /&gt;2D4) bit description&lt;/P&gt;&lt;P&gt;Table 122. Flexcomm Interface clock source select registers (FCLKSEL10, main syscon: offset 2D8) bit description&lt;/P&gt;&lt;P&gt;Obviously, the address of FCLKSEL0-9 and FCLKSEL10 are continuous, but the engineers do not compute the address, so they define the&amp;nbsp; FCLKSEL10 independently as the UM.&amp;nbsp; But It does not take effect on the function and performance of the code.&lt;/P&gt;&lt;P&gt;Anyway, I will tell the firmware team of the question.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;XiangJun Rong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Mar 2020 09:52:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/CMSIS-FCLKSEL10-LPC54018/m-p/1018933#M39855</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2020-03-26T09:52:44Z</dc:date>
    </item>
    <item>
      <title>Re: CMSIS FCLKSEL10 LPC54018</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/CMSIS-FCLKSEL10-LPC54018/m-p/1018934#M39856</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi XiangJun&lt;/P&gt;&lt;P&gt;Good point - that explains whay this register has a different name. I think it is best to keep the situation as is, because otherwise you could end up by setting the register the same as the others which will end up in a wrong configuration. The registers are not the same!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="text-decoration: underline;"&gt;&lt;EM&gt;&lt;STRONG&gt;Suggestion:&lt;/STRONG&gt;&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Don't change anything and keep things the way they are.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your valuable input and making me aware of this.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Dani&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Mar 2020 10:54:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/CMSIS-FCLKSEL10-LPC54018/m-p/1018934#M39856</guid>
      <dc:creator>danielgull</dc:creator>
      <dc:date>2020-03-26T10:54:30Z</dc:date>
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