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    <title>topic LPC55S69 : wakeup due SPI3 in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-wakeup-due-SPI3/m-p/1008304#M39547</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI3 can be used as wakeup source for exit from PowerDown mode. And it works fine.&lt;/P&gt;&lt;P&gt;But RX fifo has size 8 items only and wakeup take &amp;gt; 350 us.&lt;/P&gt;&lt;P&gt;It means , MCU can't receive any more bytes until SPI ISR can be processed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So I shouln't expect if more than 8 items will be in Fifo until exit from PowerDown is fully completed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is this so ? Or for wakeup more RX fifo can be allocated some how ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Eugene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 27 Jan 2020 19:05:55 GMT</pubDate>
    <dc:creator>EugeneHiihtaja</dc:creator>
    <dc:date>2020-01-27T19:05:55Z</dc:date>
    <item>
      <title>LPC55S69 : wakeup due SPI3</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-wakeup-due-SPI3/m-p/1008304#M39547</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI3 can be used as wakeup source for exit from PowerDown mode. And it works fine.&lt;/P&gt;&lt;P&gt;But RX fifo has size 8 items only and wakeup take &amp;gt; 350 us.&lt;/P&gt;&lt;P&gt;It means , MCU can't receive any more bytes until SPI ISR can be processed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So I shouln't expect if more than 8 items will be in Fifo until exit from PowerDown is fully completed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is this so ? Or for wakeup more RX fifo can be allocated some how ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Eugene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Jan 2020 19:05:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-wakeup-due-SPI3/m-p/1008304#M39547</guid>
      <dc:creator>EugeneHiihtaja</dc:creator>
      <dc:date>2020-01-27T19:05:55Z</dc:date>
    </item>
    <item>
      <title>Re: LPC55S69 : wakeup due SPI3</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-wakeup-due-SPI3/m-p/1008305#M39548</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, Eugene,&lt;/P&gt;&lt;P&gt;You are right that the maximum FIFO size of&amp;nbsp;LPC55S69 SPI module&amp;nbsp;is 8, this is hardware restriction, no way to increase the SPI FIFO size. &lt;/P&gt;&lt;P&gt;If more than 8 data rush into the SPI FIFO before the exit&amp;nbsp;from power-down is fully completed, some data will be lost.&lt;/P&gt;&lt;P&gt;Hope it can help you&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Xiangjun Rong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 02 Feb 2020 02:43:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-wakeup-due-SPI3/m-p/1008305#M39548</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2020-02-02T02:43:29Z</dc:date>
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