topic How to clear the System FIFO transmit in LPC Microcontrollers

How to clear the System FIFO transmit

chrisoneill — Tue, 05 Nov 2019 18:59:32 GMT

Using the 54102 with the System FIFO connected to a SPI peripheral. Each transaction leaves a few extra bytes in the transmit FIFO, want to clear before the next transaction. Set the TXFLUSH bit in the CTLSETSPI register, then TXFLUSHCLR bit in CTLCLRSPI register. TXCOUNT doesn't change and the extra bytes are transmitted out in the next SPI operation.

Re: How to clear the System FIFO transmit

Alexis_A — Fri, 08 Nov 2019 00:58:14 GMT

Hi Chris,

In which moment are you flushing the FIFO? I think it you would need to stop the transmission and reception first to not interfere with the flush of the FIFO, also, if you have the interruption enabled could be useful to dissable it before.

Let me know if this helps you.

Best Regards,

Alexis Andalon