topic Re: Memory protection unit (MPU) example for NXP LPC4078 in LPC Microcontrollers

Memory protection unit (MPU) example for NXP LPC4078

ryan_jacky — Fri, 21 Feb 2020 14:56:06 GMT

Hi everybody,

do you have any examples how to implement MPU on a NXP LPC4078?

In the UM10562 it references in chapter 40.1 to

infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/index.html

where it is described on page 4-37 in chapter "4.5 Optional Memory Protection Unit". But since this is a very general description I would be happy to have an example for LPC4078 with its memory settings.

I know it's something like

CTRL=0

>>>>>>>>

RNR

RBAR

RASR

<<<<<<<< (loop some times if needed)

CTRL=x

I found some examples for ST and Microchip on the internet but not for NXP. Do you have some or know where to find them?

Thank you!

Regards,

Daniel

Re: Memory protection unit (MPU) example for NXP LPC4078

xiangjun_rong — Mon, 24 Feb 2020 03:45:00 GMT

Hi, Jacky,

I think you can refer to the ticket for the MPU configuration. But the configuration is for LPC546xx, I think you can change it to adapt to the LPC4078.

https://community.nxp.com/docs/DOC-343992

XiangJun Rong

Re: Memory protection unit (MPU) example for NXP LPC4078

ryan_jacky — Mon, 24 Feb 2020 10:35:23 GMT

Hi XiangJun,

thank you for the example, it seems to be quite simple.

Do you know why RNR isn't set? I thought everytime RBAR and RASR is updated you need to increment RNR.

In Cortex M4 Generic User Guide I read at "4.5.3 MPU Region Number Register":

Normally, you write the required region number to this register before accessing the
MPU_RBAR or MPU_RASR. However you can change the region number by writing to the
MPU RBAR with the VALID bit set to 1, see MPU Region Base Address Register. This write
updates the value of the REGION field.

Does it automatically increment RNR by setting "VALID bit" to "1"? I only read "updating" and not "incrementing" but I think I understand it:

Since the 4 least significant bits of RBAR in the example are 0,1,2,3,4,5,6,7 this number will be written to RNR by VALID=1.

Regards,

Daniel

Re: Memory protection unit (MPU) example for NXP LPC4078

ryan_jacky — Mon, 24 Feb 2020 14:28:43 GMT

One more question:

I'd like to protect our bootloader ROM area to be not erasable. It starts at address 0 with a size of 0x8000 (32k). How should I set RASR?

In the referred example I read:

 //Region 1:
 //set up flash, ROM, SRAM ... as region 1
 //# 0x00000000 - 0x3FFFFFFF
 MPU->RBAR=0x00000011;
 MPU->RASR=0x0306E23b;‍‍‍‍‍‍‍‍‍‍

That means for RASR:

ENABLE=1

SIZE=29 (1GB?)

SRD=0xE2 (some regions disabled)

B=0 (not bufferable because ROM and not RAM?)

C=1 (but cacheable (?))

S=1 (not shareable (?)

TEX=0 (Outer and inner write-back. No write allocate.)

AP=3 (Read only, by privileged or unprivileged software)

XN=0 (instruction fetches enabled)

Which values should I select?

ENABLE=1

SIZE=14 (32k)

SRD=0 (complete bootloader region active)

B=0 (not bufferable because it's ROM?)

C=1 (cacheable yes or no?)

S=1 (not shareable yes or no?)

TEX=0 (??? What would be normal here?)

AP=3 (Read only, by privileged or unprivileged software because I only want to prevent erasing and writing to bootloader area)

XN=0 (instruction fetches enabled?)

It would be really great if you could explain correct values B,C,S,TEX for protecting the bootloader area. I don't know what would be typical values for my purpose.

Thank you!

Best regards,

Daniel

Re: Memory protection unit (MPU) example for NXP LPC4078

xiangjun_rong — Tue, 25 Feb 2020 04:27:51 GMT

Hi, Daniel,

As you know that the MPU part is feature of Cortex-M4 core, the description of TEX/C/B/S bits in RASR register in the Cortex-M4 Generic User Guide is simple, there is only a table as following figure.

I suggest you ask the ARM support so that they can give accurate, clear and detailed inf.

Sorry for not helping you

XiangJun Rong

Re: Memory protection unit (MPU) example for NXP LPC4078

ryan_jacky — Tue, 25 Feb 2020 13:34:02 GMT

Hi Xiangjun,

I already asked ARM support. After some conversation this is the answer:

On top of that, Table B3-13 in the Architecture Reference Manual although captures the same information as Table 4-45 in the Generic User Guide, to my opinion it is more helpful to choose the appropriate TEX, C and B values: first you should choose the type of memory from the "Description" column, and then use the TEX, C and B values from same row when programming MPU_RASR.
Please note that the shareability attribute and the type of memory you should be using for your ROM depends entirely on your application and on the system which the Cortex-M4 has been integrated in, and therefore I am afraid it falls under the jurisdiction of NXP's customer support.

How can I determine TEX, C, B and S values for LPC4078?

I tried it with TEX=0, B=0, C=1, S=1, but unfortunately I can't access any more with my LPC-Link2-Debugger to the device. Maybe ISP-commands will awake it but that's more complex. I don't want to produce a bunch of bricks :-)

With the brick I only get "Could not connect to core" although electrical connection is fine:

Of course I've got other new devices which work but it's not my goal to damage them all.

Regards,

Daniel