<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LPC MicrocontrollersのトピックRe: LPC55S69 : FMC configuration register</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-FMC-configuration-register/m-p/997088#M39214</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Eugene,&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;But what about enable flash prefetch and acceleration bits ?&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;They never enabled. Why ? They should work with silicon 1B.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Yes you should be able to enable these without a problem. The SDK examples are not designed to show the optimum behavior, instead we provide base examples that show how the peripherals should work. Though any additional modifications to optimize or customize should be made by customers.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;How to handle those ?&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Can I enable those at the same time when FLASHTIM is changed ?&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;You may enable them as you mention. However please consider the following points.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_5.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/94517i5865280B9525518F/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_5.png" alt="pastedImage_5.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Please confirm the revision you are working with and disable the prefetch bit must be disabled prior to executing flash commands.&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Sabina&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 19 Nov 2019 15:36:22 GMT</pubDate>
    <dc:creator>Sabina_Bruce</dc:creator>
    <dc:date>2019-11-19T15:36:22Z</dc:date>
    <item>
      <title>LPC55S69 : FMC configuration register</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-FMC-configuration-register/m-p/997087#M39213</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I can see in all examples in SDK is only&amp;nbsp;FLASHTIM is set .&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But what about enable flash prefetch and acceleration bits ?&lt;/P&gt;&lt;P&gt;They never enabled. Why ? They should work with silicon 1B.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;How to handle those ?&lt;/P&gt;&lt;P&gt;Can I enable those at the same time when FLASHTIM is changed ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Should I invalidate/flush those caches when use Flash API from Bootrom ?&lt;/P&gt;&lt;P&gt;Or when I encrypt/decrypt on fly if PRINCE peripheral is in use.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In K82 time it was always separate API to handle those issues.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Eugene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 15 Nov 2019 12:18:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-FMC-configuration-register/m-p/997087#M39213</guid>
      <dc:creator>EugeneHiihtaja</dc:creator>
      <dc:date>2019-11-15T12:18:45Z</dc:date>
    </item>
    <item>
      <title>Re: LPC55S69 : FMC configuration register</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-FMC-configuration-register/m-p/997088#M39214</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Eugene,&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;But what about enable flash prefetch and acceleration bits ?&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;They never enabled. Why ? They should work with silicon 1B.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Yes you should be able to enable these without a problem. The SDK examples are not designed to show the optimum behavior, instead we provide base examples that show how the peripherals should work. Though any additional modifications to optimize or customize should be made by customers.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;How to handle those ?&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Can I enable those at the same time when FLASHTIM is changed ?&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;You may enable them as you mention. However please consider the following points.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_5.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/94517i5865280B9525518F/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_5.png" alt="pastedImage_5.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Please confirm the revision you are working with and disable the prefetch bit must be disabled prior to executing flash commands.&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Sabina&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 19 Nov 2019 15:36:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-FMC-configuration-register/m-p/997088#M39214</guid>
      <dc:creator>Sabina_Bruce</dc:creator>
      <dc:date>2019-11-19T15:36:22Z</dc:date>
    </item>
    <item>
      <title>Re: LPC55S69 : FMC configuration register</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-FMC-configuration-register/m-p/997089#M39215</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sabina !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes, I have A2 board revision and expect there 1B version of bootloader.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Eugene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Nov 2019 06:19:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-FMC-configuration-register/m-p/997089#M39215</guid>
      <dc:creator>EugeneHiihtaja</dc:creator>
      <dc:date>2019-11-20T06:19:33Z</dc:date>
    </item>
  </channel>
</rss>

