LPC MicrocontrollersのトピックRe: LPC55S69 : Core0 and Core1 debug traces

LPC55S69 : Core0 and Core1 debug traces

EugeneHiihtaja — Fri, 01 Nov 2019 13:21:14 GMT

Hello !

I think it is not possible to share HW efficiently between 2 Cores and I can see in examples you promote different UARTs for traces in case of multiple cores usage.

Can sharing be done by using Mutex mechanism what is used if need to update shared SRAM memory in case of Mailbox usage ?

Can SWO traces be used on Core1 ?

Is any other solution when one peripheral can be shared to both cores without waiting overhead ?

Regards,

Eugene

Re: LPC55S69 : Core0 and Core1 debug traces

ZhangJennie — Tue, 05 Nov 2019 10:19:01 GMT

Hi Eugene,

SWO can be used to trace M33 core on MCUXpresso IDE v11.0.1.

With the dual-core running mode, they need to communicate with each other. The LPC55xx/LPC55Sxx provides a simple means called Inter-CPU Mailbox mechanism which has the following features:
• Provides a means Inter-Processor Communication, allowing multiple CPUs to share resources and communicate with each other in a simple manner.
• Each CPU can cause up to thirty-two user defined interrupts to its partner.
• Each CPU can claim a shared resource if it is available.
• Provides a mutual exclusion configuration for the communication handshake.

we have mailbox usage demo under SDK:

SDK_2.6.x_LPCXpresso55S69\boards\lpcxpresso55s69\driver_examples\mailbox

and also multicore demo under

boards\lpcxpresso55s69\multicore_examples

I suggest you read this document "AN12335 LPC55xx/LPC55Sxx Dual Core Communication" before you implement your dual core project:

https://www.nxp.com/docs/en/application-note/AN12335.pdf

Have a great day,
Jun Zhang

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Re: LPC55S69 : Core0 and Core1 debug traces

EugeneHiihtaja — Tue, 05 Nov 2019 11:10:10 GMT

Hi Jun Zhang !

So basically it is no any special mechanism for traces for dual core.

I should use 2 different UARTs or UART and SWO or use Mutex mechanism for share one peripheral for debug trace purposes.

Is this so ?

Regards,

Eugene

Re: LPC55S69 : Core0 and Core1 debug traces

ZhangJennie — Wed, 06 Nov 2019 01:47:28 GMT

Yes, correct.