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    <title>LPC Microcontrollers中的主题 Re: LPC55S69 : Core1 and FLEXCOM2</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991215#M39027</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Felipe !&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Could you clarify dependencies between cores in case of power management.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Looks like cores are dependant and power management APIs can be called from Core0 only and wakeup sources affects both cores some how.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;In make case I should RUN Core0 at 150Mhz for some short times and RTOS will put it to SleepMode sometimes and at known time to Power-down mode to conserve power.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Due Flexcomm 3 and few GPIO pins what are part of GINT0 , Core0 will wakeup sometimes to RUN mode from Power-Down mode.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Looks like it should work .&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;But what about Core1 behaviour while Core0 change power states ? Does it follow ?&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;I really expect that Core1 will be clocked by FRO1Mhz ( or FRO12Mhz) and can RUN or Sleep mode only.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;It can poll some I2C interface sometimes and serve output of some individual pins.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;But looks like it will be go to powerdown mode due Core0.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;But it is written that Core1 can go to Sleep mode only.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;So basically when I would like to run Core1 I should keep Core0 at list in Deep-sleep mode.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;So all wakeup sources wakeup both Cores to RUN mode and I should put Core0 to Deep-Sleep asap and continue my operation on Core1 if need.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;And if I need scheduled wakeup for Core1 and I can use RTC, OS event or other timers. What is recommended.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Core1 communicate to Core0 by using MAILBOX and it should always work becouse Core0 can't be in Powerdown if Core1 send interrupts.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Could you suggest what is the best power model in this case ?&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;How wakeup sources can wakeup both cores if GINT0 routed to Core0 and GINT1 to Core1 for example.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Eugene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 05 Nov 2019 10:50:41 GMT</pubDate>
    <dc:creator>EugeneHiihtaja</dc:creator>
    <dc:date>2019-11-05T10:50:41Z</dc:date>
    <item>
      <title>LPC55S69 : Core1 and FLEXCOM2</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991213#M39025</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello !&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Can I use I2C2 interface with speed 100/400kHz from Core1 when Core0 in PowerDown mode ?&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;I expect Core1 running at 1Mhz by using FRO_1MHZ clock and use FRO_1M or FROM_12M for clocking I2C interface.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Is this kind of configuration possible ?&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Eugene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Oct 2019 13:45:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991213#M39025</guid>
      <dc:creator>EugeneHiihtaja</dc:creator>
      <dc:date>2019-10-31T13:45:43Z</dc:date>
    </item>
    <item>
      <title>Re: LPC55S69 : Core1 and FLEXCOM2</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991214#M39026</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Eugene,&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Sorry for my late reply.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Please check the below statement from reference manual (chapter 13.2.3).&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt; &lt;EM&gt;The power-down mode affects the entire system, the clock to all CPUs and peripheral is shut down and, if not configured, the peripherals in power domains PD_SYSTEM and PD_AO receive no internal clocks.&lt;/EM&gt;&lt;/BLOCKQUOTE&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;This means the I2C will be disabled from your entire system and the only way to left I2C running in power-down will be if you use Flexcomm3 as stated in reference manual (chapter 13.3.5).&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;   &lt;P&gt;&lt;EM&gt;GPIO group interrupts, selected serial peripherals in Flexcomm3 (SPI, I2C, USART), RTC, OS Event Timers and analog comparator can be left running.&lt;/EM&gt;&lt;/P&gt; &lt;/BLOCKQUOTE&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Hope it helps!&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Felipe&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Nov 2019 20:59:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991214#M39026</guid>
      <dc:creator>FelipeGarcia</dc:creator>
      <dc:date>2019-11-04T20:59:47Z</dc:date>
    </item>
    <item>
      <title>Re: LPC55S69 : Core1 and FLEXCOM2</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991215#M39027</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Felipe !&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Could you clarify dependencies between cores in case of power management.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Looks like cores are dependant and power management APIs can be called from Core0 only and wakeup sources affects both cores some how.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;In make case I should RUN Core0 at 150Mhz for some short times and RTOS will put it to SleepMode sometimes and at known time to Power-down mode to conserve power.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Due Flexcomm 3 and few GPIO pins what are part of GINT0 , Core0 will wakeup sometimes to RUN mode from Power-Down mode.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Looks like it should work .&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;But what about Core1 behaviour while Core0 change power states ? Does it follow ?&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;I really expect that Core1 will be clocked by FRO1Mhz ( or FRO12Mhz) and can RUN or Sleep mode only.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;It can poll some I2C interface sometimes and serve output of some individual pins.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;But looks like it will be go to powerdown mode due Core0.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;But it is written that Core1 can go to Sleep mode only.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;So basically when I would like to run Core1 I should keep Core0 at list in Deep-sleep mode.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;So all wakeup sources wakeup both Cores to RUN mode and I should put Core0 to Deep-Sleep asap and continue my operation on Core1 if need.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;And if I need scheduled wakeup for Core1 and I can use RTC, OS event or other timers. What is recommended.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Core1 communicate to Core0 by using MAILBOX and it should always work becouse Core0 can't be in Powerdown if Core1 send interrupts.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Could you suggest what is the best power model in this case ?&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;How wakeup sources can wakeup both cores if GINT0 routed to Core0 and GINT1 to Core1 for example.&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;Eugene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Nov 2019 10:50:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991215#M39027</guid>
      <dc:creator>EugeneHiihtaja</dc:creator>
      <dc:date>2019-11-05T10:50:41Z</dc:date>
    </item>
    <item>
      <title>Re: LPC55S69 : Core1 and FLEXCOM2</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991216#M39028</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Eugene,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Some power modes affects both cores such power-down mode. This power mode shuts down clocks and peripherals for all CPUs just as the UM indicates. So if you want to send Core0 to power-down mode and Core1 to sleep or run mode will not be possible.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If you want to keep core1 in run mode you can use sleep mode in core0 as it only affects the relevant CPU.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please refer to my colleague reply in this thread.&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/thread/516472#comment-1228975"&gt;https://community.nxp.com/thread/516472#comment-1228975&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Felipe&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 06 Nov 2019 17:23:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC55S69-Core1-and-FLEXCOM2/m-p/991216#M39028</guid>
      <dc:creator>FelipeGarcia</dc:creator>
      <dc:date>2019-11-06T17:23:14Z</dc:date>
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