topic Re: LPC55S69 : nIRQ pin allocation in LPC Microcontrollers

LPC55S69 : nIRQ pin allocation

EugeneHiihtaja — Thu, 31 Oct 2019 12:57:14 GMT

Hi !

on page of UM 207-209 I can read this kind of recommendations:

The bootloader also supports the active notification pin (nIRQ pin) to notify the host
processor it is busy or ready for new commands/data. See below figure for the typical
physical connection between the host and the bootloader device.

....

To accelerate the SPI transfer between the host and the bootloader, the bootloader
provides an active notification pin known as the nIRQ pin, it can be enabled by the
SetProperty command. Once being enabled, the host needs to wait until it sees a negative
edge on the nIRQ pin before reading any data from the bootloader, and it needs to wait
until the nIRQ pin is high before sending any data to the bootloader.

But it is not clear what exact GPIO pin can be used for those purposes. And Exact format of message for configure it.

Do you have more info about it ?

Regards,

Eugene

Re: LPC55S69 : nIRQ pin allocation

Alexis_A — Fri, 01 Nov 2019 23:26:51 GMT

Hi Eugene,

As you mention, in the reference manual doesn't explain which pin is the nIRQ, in previous LPC the same ISP pin was used as nIRQ. So maybe is the same with this. I will test this to confirm this information

Best Regards,

Alexis Andalon

Re: LPC55S69 : nIRQ pin allocation

EugeneHiihtaja — Sun, 03 Nov 2019 09:05:09 GMT

Hi Alexis !

Could it be possible to also give recoomendation about SPI transfer speed and data packet what is optimal for ISP flashing.

Flash memory have limited write/erase timimg and dosn't have sense to deliver data faster.

So if no any nIRQ pin what is normal speed of flashing can be visible ?

From other side , flashing should be as fast as possible for save time in production.

Regards,

Eugene

Re: LPC55S69 : nIRQ pin allocation

Alexis_A — Fri, 08 Nov 2019 22:50:47 GMT

Hi Eugene,

I found how it works this pin.

The nIRQ pin is configurable. It can be configured by blhost command as shown below.

The details can be found in UM and blhost User's Guide.pdf (located at SDK/middleware/mcu-boot/doc).

Also, the configuration need it for the SPI should be CPOL = 1, CPHA = 1 and the baudrate should not be higher than 2000 kbit/s.

I hope this helps you.

Best Regards,

Alexis Andalon

Re: LPC55S69 : nIRQ pin allocation

EugeneHiihtaja — Mon, 11 Nov 2019 07:10:09 GMT

Hi Alexis !

So basically any GPIO pin ( from port 0 or 1) can play this role ?

Can be reuse ISP pin ? In this case it should be reinitialized by bootloader from input to output and may be it is locked by bootloader

as input only.

Regards,

Eugene

Re: LPC55S69 : nIRQ pin allocation

Alexis_A — Mon, 11 Nov 2019 18:11:09 GMT

Hi Eugene,

This should not affect the bootloader since after a reset the bootloader will return to its original state so the pin will be available after a reset.

Best Regards,

Alexis Andalon