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    <title>topic LPC54608 TTL CMOS input pin in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54608-TTL-CMOS-input-pin/m-p/987199#M38923</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;LPC54xxx.pdf has the following description&lt;/P&gt;&lt;P&gt;PIO0_23&lt;BR /&gt;[4]5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.&lt;/P&gt;&lt;P&gt;PIO3_18&lt;BR /&gt;[2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if VDD present; if VDD not present, do not exceed 3.6 V); provides digital I/O&amp;nbsp;functions with TTL levels and hysteresis; normal drive strength. See Figure 43. Pulse width of spikes or glitches suppressed by input&amp;nbsp;filter is from 3 ns to 16 ns (simulated value).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does this description indicate that PIO3_18 can input TTL signal?&lt;/P&gt;&lt;P&gt;Can PIO3_18 distinguish between H and L of CMOS and TTL?&lt;/P&gt;&lt;P&gt;PIO0_23 can distinguish between H and L of CMOS, but can't distinguish between H and L of TTL?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 04 Mar 2020 15:24:54 GMT</pubDate>
    <dc:creator>実奥山</dc:creator>
    <dc:date>2020-03-04T15:24:54Z</dc:date>
    <item>
      <title>LPC54608 TTL CMOS input pin</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54608-TTL-CMOS-input-pin/m-p/987199#M38923</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;LPC54xxx.pdf has the following description&lt;/P&gt;&lt;P&gt;PIO0_23&lt;BR /&gt;[4]5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.&lt;/P&gt;&lt;P&gt;PIO3_18&lt;BR /&gt;[2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if VDD present; if VDD not present, do not exceed 3.6 V); provides digital I/O&amp;nbsp;functions with TTL levels and hysteresis; normal drive strength. See Figure 43. Pulse width of spikes or glitches suppressed by input&amp;nbsp;filter is from 3 ns to 16 ns (simulated value).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does this description indicate that PIO3_18 can input TTL signal?&lt;/P&gt;&lt;P&gt;Can PIO3_18 distinguish between H and L of CMOS and TTL?&lt;/P&gt;&lt;P&gt;PIO0_23 can distinguish between H and L of CMOS, but can't distinguish between H and L of TTL?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Mar 2020 15:24:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54608-TTL-CMOS-input-pin/m-p/987199#M38923</guid>
      <dc:creator>実奥山</dc:creator>
      <dc:date>2020-03-04T15:24:54Z</dc:date>
    </item>
    <item>
      <title>Re: LPC54608 TTL CMOS input pin</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54608-TTL-CMOS-input-pin/m-p/987200#M38924</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, &lt;A _jive_internal="true" data-content-finding="Community" data-userid="309825" data-username="実奥山" href="https://community.nxp.com/people/実奥山"&gt;実奥山&lt;/A&gt; ,&lt;/P&gt;&lt;P&gt;For the digital input voltage, the processor do not care about whether it is CMOS or TTL logic, pls refer to following section pin characteristics in data sheet of LPC546xx&lt;/P&gt;&lt;P&gt;The logic voltage is dependent on the VDD voltage, the voltage which is regarded as logic 1 is from 1.5V to 5V with the condition 1.71V&amp;lt;VDD&amp;lt;2.7V, the voltage which is regarded as logic 1 is from 2.0V to 5V with the condition 2.7V&amp;lt;VDD&amp;lt;3.6V.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The logic voltage is dependent on the VDD voltage, the voltage which is regarded as logic 0 is from -0.5V to 0.4V with the condition 1.71V&amp;lt;VDD&amp;lt;2.7V, the voltage which is regarded as logic 0 is from -0.5V to 0.8V with the condition 2.7V&amp;lt;VDD&amp;lt;3.6V.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope it can help you&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;XiangJun Rong&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/103050i8CA08D369881292C/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Mar 2020 04:34:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54608-TTL-CMOS-input-pin/m-p/987200#M38924</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2020-03-05T04:34:53Z</dc:date>
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