LPC1817 EMC Interface read cycle

chase_lin — Thu, 31 Oct 2019 02:04:26 GMT

Hi NXP support team,

I got an issue about LPC1817 EMC interface read cycle. I connected the EMC(Static memory) interface to SRAM in my design. When I issued one read cycle, I got two EMC address(0x00 -> 0x01) toggle from scope as follows. It made the read data error. It should be one address in one read cycle. My EMC configuration as follows. Do you have any ideas? Thanks.

//======================================EMC Configuration===================================
LPC_EMC->STATICCONFIG0 = ( (0 << 0)    |       // Memory width 8-bit
                                                       (0 << 3)    |       // Async page mode disable
                                                       (0 << 6)    |       // Active LOW chip select
                                                       (1 << 7)    |       // Byte lane state: use WE signal
                                                       (0 << 19) );       // Disable buffer

LPC_EMC->STATICWAITWEN0 = 0x2;                 // Wait output enable: 2 delay

LPC_EMC->STATICWAITOEN0    = 0x2;                   // Wait output enable: 2 delay

LPC_EMC->STATICWAITTURN0 = 0x0;

LPC_EMC->STATICWAITPAG0 = 0x0;

LPC_EMC->STATICWAITWR0 = 0x0F;

LPC_EMC->STATICWAITRD0 = 0x0F;

LPC_EMC->CONTROL = ( (1 << 0) | //EMC Enable
(0 << 1) ); //EMC Addr non-mirror

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Re: LPC1817 EMC Interface read cycle

Sabina_Bruce — Fri, 08 Nov 2019 03:37:58 GMT

Hello Chase,

Hope you are doing well. It is possible that an EMC will perform a burst read access even when the buffer enable bit is disabled. In the case of the configurations you have provided the bit 19 of the Static Memory Configuration register that is described in table 369 of the user manual.

Burst read means that if you were meant to read register 0(even with the buffer disabled) it will read 0 and 1.

Let me know if you have further questions.

Best Regards,

Sabina

Re: LPC1817 EMC Interface read cycle

chase_lin — Wed, 22 Dec 2021 02:08:23 GMT

Hi Bruce,

So I couldn't use any methods to disable the burst read ? Thanks.

topic Re: LPC1817 EMC Interface read cycle in LPC Microcontrollers

LPC1817 EMC Interface read cycle

Re: LPC1817 EMC Interface read cycle

Re: LPC1817 EMC Interface read cycle