Implementing 6 Inputs function on PLU module

randa_zarrouk — Wed, 30 Oct 2019 10:41:59 GMT

I want to implement a function that depends on 6 Inputs and gives 8 Outputs making use of the PLU module.

everything works fine when it is about 5 inputs and 8 outputs, but when I add the 6th input, the PLU configuration tool don't accept to parse the Verilog code.

Supposedly, you write the Verilog code and imported to the configuration tool, which is going to optimize the design and then into C code. This will only be possible if the Verilog code is error free.

To make sure that there is no problem with syntax, I made a test with a code which deploys 5 inputs and 8 outputs. It was accepted and turned into C code. In the next step, I only added the 6th Input. The optimize wizard of the configuration tool didn't want to move to the next step.

Does that correlates with the fact that there are only 5 inputs for the one LUT which is the base component of the PLU module?

But even-though, still there are 6 PLU_Inputs and 25 LUTs that can be used by the wizard to implement this function.

Any idea or explanation to the meaning behind that?

The Verilog code of the envisaged function (5 Inputs/8 Outputs):

module main(R, Q, P ,O, L,N,M,K,A,B,C,D,E);

output K;
output M;
output N;
output L;
output O;
output P;
output Q;
output R;
input A;
input B;
input C;
input D;
input E;
always @(E,D,C,B,A) //D, E, F
begin
case({E,D,C,B,A})

5'b11011 : begin
K = 1'b0 ;
M = 1'b0 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end
5'b10101 : begin

K = 1'b1 ;
M = 1'b1 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end
5'b10000 : begin

K = 1'b1 ;
M = 1'b0 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b0 ;
end
5'b11110 : begin

K = 1'b0 ;
M = 1'b0 ;
N = 1'b1 ;
L = 1'b0 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end
5'b00001 : begin

K = 1'b1 ;
M = 1'b1 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b0 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end
5'b01111 : begin

K = 1'b1 ;
M = 1'b1 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b0 ;
R = 1'b1 ;
end
default : begin

K = 1'b0 ;
M = 1'b0 ;
N = 1'b0 ;
L = 1'b0 ;
O = 1'b0 ;
P = 1'b0 ;
Q = 1'b0 ;
R = 1'b0 ;
end
endcase
end

endmodule

The corresponding C code to the above Verilog code of the envisaged function (5 Inputs/8 Outputs) generated by the PLU configuration tool :

/*
* This file was generated by the PLU Config Tool.
* 6 Inputs 26 LUTs 4 flip flops and 8 outputs *
/* LUT4 (K) *
PLU->LUT[4].INP[0] = 0x00000002; /* IN2 (C) *
PLU->LUT[4].INP[1] = 0x00000001; /* IN1 (B) *
PLU->LUT[4].INP[2] = 0x00000000; /* IN0 (A) *
PLU->LUT[4].INP[3] = 0x0000003F; /* default *
PLU->LUT[4].INP[4] = 0x0000003F; /* default *
PLU->LUT_TRUTH[4] = 0xb1b1b1b1; /* K CUSTOM *
/* LUT5 (L) *
PLU->LUT[5].INP[0] = 0x00000002; /* IN2 (C) *
PLU->LUT[5].INP[1] = 0x00000001; /* IN1 (B) *
PLU->LUT[5].INP[2] = 0x00000000; /* IN0 (A) *
PLU->LUT[5].INP[3] = 0x0000003F; /* default *
PLU->LUT[5].INP[4] = 0x0000003F; /* default *
PLU->LUT_TRUTH[5] = 0xf1f1f1f1; /* L CUSTOM *
/* LUT6 (M) *
PLU->LUT[6].INP[0] = 0x00000002; /* IN2 (C) *
PLU->LUT[6].INP[1] = 0x00000001; /* IN1 (B) *
PLU->LUT[6].INP[2] = 0x00000000; /* IN0 (A) *
PLU->LUT[6].INP[3] = 0x0000003F; /* default *
PLU->LUT[6].INP[4] = 0x0000003F; /* default *
PLU->LUT_TRUTH[6] = 0xb0b0b0b0; /* M CUSTOM *
/* LUT7 (N) *
PLU->LUT[7].INP[0] = 0x00000002; /* IN2 (C) *
PLU->LUT[7].INP[1] = 0x00000001; /* IN1 (B) *
PLU->LUT[7].INP[2] = 0x00000000; /* IN0 (A) *
PLU->LUT[7].INP[3] = 0x0000003F; /* default *
PLU->LUT[7].INP[4] = 0x0000003F; /* default *
PLU->LUT_TRUTH[7] = 0xf9f9f9f9; /* N CUSTOM *
/* LUT8 (O) *
PLU->LUT[8].INP[0] = 0x00000002; /* IN2 (C) *
PLU->LUT[8].INP[1] = 0x00000001; /* IN1 (B) *
PLU->LUT[8].INP[2] = 0x00000000; /* IN0 (A) *
PLU->LUT[8].INP[3] = 0x0000003F; /* default *
PLU->LUT[8].INP[4] = 0x0000003F; /* default *
PLU->LUT_TRUTH[8] = 0xe9e9e9e9; /* O CUSTOM *
/* LUT9 (P) *
PLU->LUT[9].INP[0] = 0x00000002; /* IN2 (C) *
PLU->LUT[9].INP[1] = 0x00000001; /* IN1 (B) *
PLU->LUT[9].INP[2] = 0x00000000; /* IN0 (A) *
PLU->LUT[9].INP[3] = 0x0000003F; /* default *
PLU->LUT[9].INP[4] = 0x0000003F; /* default *
PLU->LUT_TRUTH[9] = 0xf9f9f9f9; /* P CUSTOM *
/* LUT10 (Q) *
PLU->LUT[10].INP[0] = 0x00000002; /* IN2 (C) *
PLU->LUT[10].INP[1] = 0x00000001; /* IN1 (B) *
PLU->LUT[10].INP[2] = 0x00000000; /* IN0 (A) *
PLU->LUT[10].INP[3] = 0x0000003F; /* default *
PLU->LUT[10].INP[4] = 0x0000003F; /* default *
PLU->LUT_TRUTH[10] = 0x79797979; /* Q CUSTOM *
/* LUT11 (R) *
PLU->LUT[11].INP[0] = 0x00000002; /* IN2 (C) *
PLU->LUT[11].INP[1] = 0x00000001; /* IN1 (B) *
PLU->LUT[11].INP[2] = 0x00000000; /* IN0 (A) *
PLU->LUT[11].INP[3] = 0x0000003F; /* default *
PLU->LUT[11].INP[4] = 0x0000003F; /* default *
PLU->LUT_TRUTH[11] = 0xf8f8f8f8; /* R CUSTOM *
PLU->OUTPUT_MUX[0] = 0x00000004; /* LUT4 (K) -> K_PLU_OUT *
PLU->OUTPUT_MUX[1] = 0x00000006; /* LUT6 (M) -> M_PLU_OUT *
PLU->OUTPUT_MUX[2] = 0x00000007; /* LUT7 (N) -> N_PLU_OUT *
PLU->OUTPUT_MUX[3] = 0x00000005; /* LUT5 (L) -> L_PLU_OUT *
PLU->OUTPUT_MUX[4] = 0x00000008; /* LUT8 (O) -> O_PLU_OUT *
PLU->OUTPUT_MUX[5] = 0x00000009; /* LUT9 (P) -> P_PLU_OUT *
PLU->OUTPUT_MUX[6] = 0x0000000a; /* LUT10 (Q) -> Q_PLU_OUT *
PLU->OUTPUT_MUX[7] = 0x0000000b; /* LUT11 (R) -> R_PLU_OUT */

Now , here is:

The Verilog code of the envisaged function (6 Inputs/8 Outputs):

module main(R, Q, P ,O, L,N,M,K,A,B,C,D,E,F);

output K;
output M;
output N;
output L;
output O;
output P;
output Q;
output R;
input A;
input B;
input C;
input D;
input E;
input F;
always @(F,E,D,C,B,A) //D, E, F
begin
case({F,E,D,C,B,A})

6'b111011 : begin
K = 1'b0 ;
M = 1'b0 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end
6'b110101 : begin

K = 1'b1 ;
M = 1'b1 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end
6'b110000 : begin

K = 1'b1 ;
M = 1'b0 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b0 ;
end
6'b111110 : begin

K = 1'b0 ;
M = 1'b0 ;
N = 1'b1 ;
L = 1'b0 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end
6'b100001 : begin

K = 1'b1 ;
M = 1'b1 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b0 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end
5'b101111 : begin

K = 1'b1 ;
M = 1'b1 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b0 ;
R = 1'b1 ;
end
default : begin

K = 1'b0 ;
M = 1'b0 ;
N = 1'b0 ;
L = 1'b0 ;
O = 1'b0 ;
P = 1'b0 ;
Q = 1'b0 ;
R = 1'b0 ;
end
endcase
end
endmodule

Thank you!#

Re: Implementing 6 Inputs function on PLU module

randa_zarrouk — Thu, 31 Oct 2019 12:35:01 GMT

Hello again,

Problem fixed when I replaced the case statement with the if statement so it became:

for example:

if (A == 1 && B==1 && C==0 && D==1 && E==1 && F==0)
begin
Y = 1'b1 ; // LSB if mapped as LUT0
K = 1'b1 ;
L = 1'b1 ;
M = 1'b1 ;
N = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ; // MSB if mapped as LUT8
end

instead of :

case({F,E,D,C,B,A})

6'b111011 : begin
K = 1'b0 ;
M = 1'b0 ;
N = 1'b1 ;
L = 1'b1 ;
O = 1'b1 ;
P = 1'b1 ;
Q = 1'b1 ;
R = 1'b1 ;
end

So now my question is, why it is possible using the if statement but not possible using the case statement?

Re: Implementing 6 Inputs function on PLU module

xiangjun_rong — Fri, 08 Nov 2019 07:47:47 GMT

Hi, Randa,

As you know that the PLU is a very simple programmable module, it only has 4 flip-flops, so the compiler/synthetizer are also very simple, it does not support case instruction.

XiangJun Rong

Re: Implementing 6 Inputs function on PLU module

randa_zarrouk — Fri, 08 Nov 2019 11:33:11 GMT

Hi Xiang Jun Rong,

Thank you for your response.

Does it mean that using the case statement with 6 inputs implies the use of filpflops? Because using the case statement with 5 inputs was accepted and didn't use flipflops, it only used LUTs.

Best.

Randa

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Implementing 6 Inputs function on PLU module

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Re: Implementing 6 Inputs function on PLU module