<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LPC MicrocontrollersのトピックLPC54628 as SPI slave</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981219#M38724</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;There are two LPC54628 of which one acts as SPI Master and the other SPI Slave.&lt;/P&gt;&lt;P&gt;This is my requirement:&lt;/P&gt;&lt;P&gt;The SPI master sends 5 bytes of data in 8 bit SPI mode: the first 3 are data bytes and the 4th is checksum (XOR of first 3 bytes). After this, the master sends 8 clock cycles (5th byte) in order receive acknowledgement from the slave to know whether it received data without errors.&lt;/P&gt;&lt;P&gt;The SPI Slave receives the four bytes from the Master, calculates checksum and compares with the received checksum. If they match, the slave loads a acknowledgment signal (0xAA) which gets shifted out from the slave to the master as the master sends the 8 clock cycles.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What works:&lt;BR /&gt;The master works fine. The slave works fine till the calculation and comparison of checksum.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What doesn't work:&lt;/P&gt;&lt;P&gt;When I load the acknowledgment byte 0xAA into the SPI slave, I expect it to be shifted out to the master as the master sends 8 clock cycles in the 5th byte of a frame. But on probing, i find that the ack byte is being sent out only in the 1st byte of the next frame. What is happening? Please help.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;// Interrupt Service Routine for SPI-Slave where all action takes place&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;uint8_t SPI_Rx[5] = {0,0,0,0,0};&lt;BR /&gt;uint8_t SPI_DO_BUFFERSIZE = 0x05;&lt;BR /&gt;uint8_t slave_RxIndex = 0x05;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;void ISR_Slave_FC5_SPI_DOBoard(void){&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;if (SPI_GetStatusFlags(FC5_SPI_PERIPHERAL) &amp;amp; kSPI_RxNotEmptyFlag) {&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SPI_Rx[SPI_DO_BUFFERSIZE - slave_RxIndex] = SPI_ReadData(FC5_SPI_PERIPHERAL);&amp;nbsp;&amp;nbsp; // save to array &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;slave_RxIndex--;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;if (slave_RxIndex &amp;gt; 1U){&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // load 0x00 as MISO data until the 8 clocks are not received&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SPI_WriteData(FC5_SPI_PERIPHERAL, 0x00, 0);&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;else if (slave_RxIndex == 1U){&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;calculatedChksum = SPI_Rx[0] ^ SPI_Rx[1] ^ SPI_Rx[2] ;&amp;nbsp;&amp;nbsp; // calculate chksum by XOR of 3 bytes&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;if (calculatedChksum == SPI_Rx[3]){&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SPI_WriteData(FC5_SPI_PERIPHERAL, 0xAA, 0); // load 0xAA as ACK which will be sent out when Master sends 8 clocks during 5th byte&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;else if (slave_RxIndex == 0U){&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;slaveFinished = true;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SPI_WriteData(FC5_SPI_PERIPHERAL, 0x00, 0);&amp;nbsp;&amp;nbsp; // load 0x00 so that next frame onwards 0x00 is the MISO data&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;slave_RxIndex = 5U;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;exception return operation might vector to incorrect interrupt */&lt;BR /&gt;#if defined __CORTEX_M &amp;amp;&amp;amp; (__CORTEX_M == 4U)&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;__DSB();&lt;BR /&gt;#endif&lt;BR /&gt;}&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;// SPI Slave settings&lt;/P&gt;&lt;P&gt;const spi_slave_config_t FC5_SPI_config = {&lt;BR /&gt;&amp;nbsp; .enableSlave = true,&lt;BR /&gt;&amp;nbsp; .polarity = kSPI_ClockPolarityActiveHigh,&lt;BR /&gt;&amp;nbsp; .phase = kSPI_ClockPhaseFirstEdge,&lt;BR /&gt;&amp;nbsp; .direction = kSPI_MsbFirst,&lt;BR /&gt;&amp;nbsp; .dataWidth = kSPI_Data8Bits,&lt;BR /&gt;&amp;nbsp; .sselPol = kSPI_SpolActiveAllLow,&lt;BR /&gt;&amp;nbsp; .txWatermark = kSPI_TxFifo0,&lt;BR /&gt;&amp;nbsp; .rxWatermark = kSPI_RxFifo1&lt;BR /&gt;};&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI Master settings are near identical, with baud rate set at 50kbps. Both microcontrollers run at 96MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="scope_1 - Copy (2).bmp"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/100728i5FD10BDD313CA4B3/image-size/large?v=v2&amp;amp;px=999" role="button" title="scope_1 - Copy (2).bmp" alt="scope_1 - Copy (2).bmp" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 04 Feb 2020 10:51:54 GMT</pubDate>
    <dc:creator>aswinprabhu</dc:creator>
    <dc:date>2020-02-04T10:51:54Z</dc:date>
    <item>
      <title>LPC54628 as SPI slave</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981219#M38724</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;There are two LPC54628 of which one acts as SPI Master and the other SPI Slave.&lt;/P&gt;&lt;P&gt;This is my requirement:&lt;/P&gt;&lt;P&gt;The SPI master sends 5 bytes of data in 8 bit SPI mode: the first 3 are data bytes and the 4th is checksum (XOR of first 3 bytes). After this, the master sends 8 clock cycles (5th byte) in order receive acknowledgement from the slave to know whether it received data without errors.&lt;/P&gt;&lt;P&gt;The SPI Slave receives the four bytes from the Master, calculates checksum and compares with the received checksum. If they match, the slave loads a acknowledgment signal (0xAA) which gets shifted out from the slave to the master as the master sends the 8 clock cycles.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What works:&lt;BR /&gt;The master works fine. The slave works fine till the calculation and comparison of checksum.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What doesn't work:&lt;/P&gt;&lt;P&gt;When I load the acknowledgment byte 0xAA into the SPI slave, I expect it to be shifted out to the master as the master sends 8 clock cycles in the 5th byte of a frame. But on probing, i find that the ack byte is being sent out only in the 1st byte of the next frame. What is happening? Please help.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;// Interrupt Service Routine for SPI-Slave where all action takes place&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;uint8_t SPI_Rx[5] = {0,0,0,0,0};&lt;BR /&gt;uint8_t SPI_DO_BUFFERSIZE = 0x05;&lt;BR /&gt;uint8_t slave_RxIndex = 0x05;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;void ISR_Slave_FC5_SPI_DOBoard(void){&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;if (SPI_GetStatusFlags(FC5_SPI_PERIPHERAL) &amp;amp; kSPI_RxNotEmptyFlag) {&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SPI_Rx[SPI_DO_BUFFERSIZE - slave_RxIndex] = SPI_ReadData(FC5_SPI_PERIPHERAL);&amp;nbsp;&amp;nbsp; // save to array &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;slave_RxIndex--;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;if (slave_RxIndex &amp;gt; 1U){&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // load 0x00 as MISO data until the 8 clocks are not received&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SPI_WriteData(FC5_SPI_PERIPHERAL, 0x00, 0);&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;else if (slave_RxIndex == 1U){&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;calculatedChksum = SPI_Rx[0] ^ SPI_Rx[1] ^ SPI_Rx[2] ;&amp;nbsp;&amp;nbsp; // calculate chksum by XOR of 3 bytes&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;if (calculatedChksum == SPI_Rx[3]){&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SPI_WriteData(FC5_SPI_PERIPHERAL, 0xAA, 0); // load 0xAA as ACK which will be sent out when Master sends 8 clocks during 5th byte&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;else if (slave_RxIndex == 0U){&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;slaveFinished = true;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SPI_WriteData(FC5_SPI_PERIPHERAL, 0x00, 0);&amp;nbsp;&amp;nbsp; // load 0x00 so that next frame onwards 0x00 is the MISO data&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;slave_RxIndex = 5U;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;exception return operation might vector to incorrect interrupt */&lt;BR /&gt;#if defined __CORTEX_M &amp;amp;&amp;amp; (__CORTEX_M == 4U)&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;__DSB();&lt;BR /&gt;#endif&lt;BR /&gt;}&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;// SPI Slave settings&lt;/P&gt;&lt;P&gt;const spi_slave_config_t FC5_SPI_config = {&lt;BR /&gt;&amp;nbsp; .enableSlave = true,&lt;BR /&gt;&amp;nbsp; .polarity = kSPI_ClockPolarityActiveHigh,&lt;BR /&gt;&amp;nbsp; .phase = kSPI_ClockPhaseFirstEdge,&lt;BR /&gt;&amp;nbsp; .direction = kSPI_MsbFirst,&lt;BR /&gt;&amp;nbsp; .dataWidth = kSPI_Data8Bits,&lt;BR /&gt;&amp;nbsp; .sselPol = kSPI_SpolActiveAllLow,&lt;BR /&gt;&amp;nbsp; .txWatermark = kSPI_TxFifo0,&lt;BR /&gt;&amp;nbsp; .rxWatermark = kSPI_RxFifo1&lt;BR /&gt;};&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI Master settings are near identical, with baud rate set at 50kbps. Both microcontrollers run at 96MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="scope_1 - Copy (2).bmp"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/100728i5FD10BDD313CA4B3/image-size/large?v=v2&amp;amp;px=999" role="button" title="scope_1 - Copy (2).bmp" alt="scope_1 - Copy (2).bmp" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Feb 2020 10:51:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981219#M38724</guid>
      <dc:creator>aswinprabhu</dc:creator>
      <dc:date>2020-02-04T10:51:54Z</dc:date>
    </item>
    <item>
      <title>Re: LPC54628 as SPI slave</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981220#M38725</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, Aswin,&lt;/P&gt;&lt;P&gt;I think there is a bug when the SPI module is used as slave device and transmitter, the workaround is to fill the 8 level transmitter FIFO with dummy data before the SPI slave transmits any data.&lt;/P&gt;&lt;P&gt;Hope it can help you&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;XiangJun Rong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Feb 2020 09:08:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981220#M38725</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2020-02-05T09:08:58Z</dc:date>
    </item>
    <item>
      <title>Re: LPC54628 as SPI slave</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981221#M38726</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I was able to solve the issue by setting SPI_ClockPhase as &lt;A class="" href="https://mcuxpresso.nxp.com/api_doc/dev/116/group__spi__driver.html#gga9ad313685ade497f5cbcb71c74a1b4dca18a98985c1f7dd56175e4a2724db3675"&gt;kSPI_ClockPhaseSecondEdge&lt;/A&gt; instead of FirstEdge.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Feb 2020 19:19:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981221#M38726</guid>
      <dc:creator>aswinprabhu</dc:creator>
      <dc:date>2020-02-05T19:19:32Z</dc:date>
    </item>
    <item>
      <title>Re: LPC54628 as SPI slave</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981222#M38727</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, Aswin,&lt;/P&gt;&lt;P&gt;If you toggle the /SS pin of slave SPI for each data transfer, the bug does not appear.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;XiangJun Rong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Feb 2020 01:04:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-as-SPI-slave/m-p/981222#M38727</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2020-02-06T01:04:45Z</dc:date>
    </item>
  </channel>
</rss>

