LPC55S66 : flash memory banks ?

EugeneHiihtaja — Tue, 29 Oct 2019 09:48:36 GMT

Hello !

Does Core1 is not able to run from Flash memory in any case or only if Core0 is not use it ?

In almost all SDK examples, Core 1 code is executed from RAM only.

So Flash memory is monolithic and not banked . It also mean that write/erase operation is stall execution of Core0 ?

But all flash API are located in ROM and it is not visible how all interrupts are enabled and disabled.

Could you clarify Flash memory behaviour in case of sharing it between Core0&1 and write/erase operations.

Regards,

Eugene

Re: LPC55S66 : flash memory banks ?

Alice_Yang — Tue, 29 Oct 2019 14:59:10 GMT

Hello Eugene Hiihtaja ,

For LPC55S66 there is only one flash bank, so we can not running two or more cores main code on one storage bank, because if both core need catch data or command, flash can not response both core request, the core will be stopped and generate fault. Core1's app code storaged in Flash, once power-up, core0 will be startup first, then copied the core1 image into SRAM area and run core1.

Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

LPC MicrocontrollersのトピックLPC55S66 : flash memory banks ?

LPC55S66 : flash memory banks ?

Re: LPC55S66 : flash memory banks ?