LPC MicrocontrollersのトピックRe: LPC55S66 : Mailbox interrupt

LPC55S66 : Mailbox interrupt

EugeneHiihtaja — Tue, 29 Oct 2019 09:45:23 GMT

Hello !

in UM in table 293 , WAKEUP_WAKEUP_MAILBOX Mailbox interrupt is mentioned. But it is not clear if it can wakeup Core 0 from Power-down mode.

What is best way to wakeup Core0 from Power-down mode from Core1 side ?

What kind of interrupt(s) can be used for do it ?

Regards,

Eugene

Re: LPC55S66 : Mailbox interrupt

Sabina_Bruce — Thu, 31 Oct 2019 01:50:16 GMT

Hello Eugene,

Hope you are doing well. The mailbox interrupt can wake up if the core is in sleep mode, however not from power down, deep power down or deep sleep.

If you would like to wake up from power down you can consider the following:

• Using a reset from the RESET pin.

All wake-up events (other than reset) must be enabled via the power API.

• Using a wake-up signal from any of the serial peripherals in Flexcomm3.

• Using the analog comparator.

• GPIO group interrupt signal.

• RTC alarm signal or wake-up signal.

• OS Event Timer.

To test different wake up signals with the different power modes. I'd recommend to use our lpc_power_management example from our SDK.

Best Regards,

Sabina

Re: LPC55S66 : Mailbox interrupt

EugeneHiihtaja — Thu, 31 Oct 2019 07:38:32 GMT

Hello Sabina !

I can see those wakeups for Core 0 in powerAPI tables.

But what really can be used by Core1 for wakeup Core0 as fast as possible ?

May be I can write to some rigisters for simulate RTC alarm or OS event.

I mean how Core1 by SW only can wakeup Core0 from PowerDown mode ?

Those peripherals can do it but can Core1 use those for wakeup Core0.

Regards,

Eugene

Re: LPC55S66 : Mailbox interrupt

Sabina_Bruce — Mon, 04 Nov 2019 15:22:56 GMT

Hi Eugene,

Hope you are doing well. I am not sure if I understand what you are trying to achieve.

In power down mode, the clock to all CPUs is turned off, so it will not be possible to wake up core 0 through core 1. As I mentioned in my previous post in order to wake up the core you have the different methods listed above.

In sleep-mode, you may sleep one core or the other and then you are able to use the mailbox interrupt to wake up the core 0 via the core 1.

Table 305 lists how you are able to wake up the system with the interrupts and in which power mode these can be enabled.

If I am misunderstanding your question, please clarify so that I may better assist you.

Best Regards,

Sabina

Re: LPC55S66 : Mailbox interrupt

EugeneHiihtaja — Mon, 04 Nov 2019 17:17:27 GMT

Hi Sabina !

in New UM, Malbox interrupt is already highlighted in this case.

In my case Core0 wakeup from Power-down very rear and also all peripherals will be accessible from Core 0 only.

I think safest way is wakeup Core0 via GPIO line what can be part of GINT0 group.

In this case Core 1 can toggle other pin ( it connected to abobo one) and wakeup Core0.

Can Core1 program OS_Evnt timer and it will wakeup Core0 asap ?

Regards,

Eugene

Re: LPC55S66 : Mailbox interrupt

Sabina_Bruce — Wed, 06 Nov 2019 16:21:50 GMT

Hi Eugene,

To clarify, in power down mode both core 0 and core 1 are powered down. Core 1 cannot wake up core 0, because it is also powered off. The clocks to both core 0 and core 1 are turned off.

The interrupts you mention will wake up the system(core 0 and core 1).

If you would like to turn off core 0 only and wake up with core 1, this is Sleep Mode.

Sleep: Sleep-mode saves a significant amount of power by stopping CPU execution without affecting peripherals or requiring significant wake-up time. The sleep-mode affects the relevant CPU only. The clock to the CPU is shut off. Peripherals and memories are active and operational.(Can be one CPU or both CPU)

Best Regards,

Sabina

Re: LPC55S66 : Mailbox interrupt

EugeneHiihtaja — Wed, 06 Nov 2019 19:42:53 GMT

Hi Sabina !

I think it is clear but what about calling of Powermanagement API ?

Can any core call these or only Core0 ?

But it is not so clear why is done like this ? As usually other slave Core should run in lower power mode and it have mode benefit.

But now Core 1 looks as coprocessor what need to boost performance of some specific libraries.

Regards,

Eugene