LPC MicrocontrollersのトピックRe: LPC55S69 : SRAMX_3 usage for CPU retention data

LPC55S69 : SRAMX_3 usage for CPU retention data

EugeneHiihtaja — Mon, 03 Feb 2020 18:34:23 GMT

Hi !

In UM mentioned that is possible to select SRAMX area for CPU retention :

"If CPU retention used in power-down mode, SRAMX_2 (0x1400 6000 to 0x1400 65FF) is
used (total 1.5 KB) by default in power API and this is user configurable within SRAMX_2 and SRAMX_3.

But it is not clear how-to configure in use SRAMX_3 area instead of SRAMX_2 for save CPU retention data.

SRAM_X3 should be retained if it used and it can be configured bit how-to redirect CPU data is not clear.

Regards,

Eugene

Re: LPC55S69 : SRAMX_3 usage for CPU retention data

ZhangJennie — Wed, 05 Feb 2020 11:00:24 GMT

Eugene Hiihtaja

We use ROM API POWER_EnterDeepPowerDown to configure in use SRAMX area.

The sram_retention_ctrl parameter defines which SRAM instances will be put in Retention mode during deep power-down. SRAM instances in Retention mode do not lose their content. SRAM instances that are not required to be put in Retention mode during deep power-down will be shut down (meaning their content will be lost upon wake-up from deep
power-down.

Have a great day,
Jun Zhang

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Re: LPC55S69 : SRAMX_3 usage for CPU retention data

EugeneHiihtaja — Wed, 05 Feb 2020 12:00:08 GMT

Hi ZhangJennie‌ !

I'm using POWER_EnterPowerDown() API and it is quite clear what exact SRAM areas should be retain by specifying mask sram_retention_ctrl . 0x7FFF is cover whole SRAM space.

BUT

in UM:

"If CPU retention used in power-down mode, SRAMX_2 (0x1400 6000 to 0x1400 65FF) is
used (total 1.5 KB) by default in power API and this is user configurable within SRAMX_2 and SRAMX_3.

If CPU retention used in power-down
mode, SRAMX_2 (0x1400 6000 to 0x1400 65FF) is
used (total 1.5 KB) by default in power API and this is
user configurable within SRAMX_2 and SRAMX_3.

SRAMX ( 0x1400 0000 - 0x1400 7FFF, size 32KB )

SRAMX_0 - 0x1400 0000 - 0x1400 1FFF
SRAMX_1 - 0x1400 2000 - 0x1400 3FFF
SRAMX_2 - 0x1400 4000 - 0x1400 5FFF
SRAMX_3 - 0x1400 6000 - 0x1400 7FFF, --> 0x1400 6000 to 0x1400 65FF ( CPU retention area )

So really it is ín SRAMX_3 already but can be in X_2 as well ?

Or how I should understand CPU retention area location ?

Regards,

Eugene

Re: LPC55S69 : SRAMX_3 usage for CPU retention data

ZhangJennie — Thu, 06 Feb 2020 08:50:58 GMT

Eugene,

The size of RAM_X0 to RAM_X3 is not same, see table 307 in UM

So 0x1400 6000 to 0x1400 65FF ( CPU retention area ) is inside RAM_X2 instance.

Have a great day,
Jun Zhang

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Re: LPC55S69 : SRAMX_3 usage for CPU retention data

EugeneHiihtaja — Thu, 06 Feb 2020 09:08:59 GMT

Hi ZhangJennie‌ !

I need large contiguous area of SRAMX and would like to move CPU retention area to SRAM_X3

, like it mentioned in UM.

"If CPU retention used in power-down mode, SRAMX_2 (0x1400 6000 to 0x1400 65FF) is
used (total 1.5 KB) by default in power API and this is user configurable within SRAMX_2 and SRAMX_3.

How it can be done ?

Regards,

Eugene

Re: LPC55S69 : SRAMX_3 usage for CPU retention data

ZhangJennie — Thu, 06 Feb 2020 10:57:39 GMT

config sram_retention_ctrl is used to set retained RAM.

for example, with below code, RAM instances RAM_X2 & RAM_X3 content will be retained.

sram_retention_ctrl = LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 |
LOWPOWER_SRAMRETCTRL_RETEN_RAMX3;

this chip doesn't have feature to set large contiguous area of SRAMX for CPU retention area.

Re: LPC55S69 : SRAMX_3 usage for CPU retention data

EugeneHiihtaja — Thu, 06 Feb 2020 11:08:54 GMT

Hi ZhangJennie‌ !

So this memory area : SRAMX_2 (0x1400 6000 to 0x1400 65FF) is hardcoded for CPU retention data in case of PowerDown mode

and can't be changed. Is this so ?

Regards,

Eugene

Re: LPC55S69 : SRAMX_3 usage for CPU retention data

ZhangJennie — Thu, 06 Feb 2020 11:13:05 GMT

yes, correct.

Re: LPC55S69 : SRAMX_3 usage for CPU retention data

EugeneHiihtaja — Thu, 06 Feb 2020 12:28:02 GMT

Hi ZhangJennie‌ !

But for what reason SRAMX_3 area is mentioned there ?

It should be reason or this is typo or nondocumented feature ?

Moving CPU retention data from SRAMX2 to 3 will bring extra 4KB of SRAM and it good benefit.

Regrads,

Eugene

Re: LPC55S69 : SRAMX_3 usage for CPU retention data

ZhangJennie — Thu, 06 Feb 2020 13:25:39 GMT

UM is right. not typo