LPC1778 - problems with SRAM byte read access

lpcware — Wed, 15 Jun 2016 17:47:46 GMT

Content originally posted in LPCWare by rda on Wed Mar 25 02:28:45 MST 2015
Hello,

currently I am trying to connect an ISSI IS62WV25616BLL SRAM to an LPC1778. The SRAM is working if I access WORD (16-bit) or DWORD (32-bit) data. BYTE (8-bit) access causes an invalid value upon the second (!) read access, as the following code illustrates (the heap is on the SRAM):

unsigned char *cptr = (unsigned char *)malloc(2);
cptr[0] = 0xDE;
print("cptr[0]=0x%02X\n", cptr[0]);
print("cptr[0]=0x%02X\n", cptr[0]);
free(cptr);

unsigned short *sptr = (unsigned short *)malloc(4);
sptr[0] = 0xCAFE;
print("sptr[0]=0x%04X\n", sptr[0]);
print("sptr[0]=0x%04X\n", sptr[0]);
free(sptr);

unsigned int *iptr = (unsigned int *)malloc(8);
iptr[0] = 0xDEADBEEF;
print("iptr[0]=0x%08X\n", iptr[0]);
print("iptr[0]=0x%08X\n", iptr[0]);
free(iptr);

The following output is produced:

cptr[0]=0xDE
cptr[0]=0x06
sptr[0]=0xCAFE
sptr[0]=0xCAFE
iptr[0]=0xDEADBEEF
iptr[0]=0xDEADBEEF

As you can see the data value after the second BYTE read access is corrupted while both the WORD and DWORD values are correct.

The SRAM is connected to the LPC1778 as follows:

P3.00[EMC_D0]    IO3
P3.01[EMC_D1]    IO4
P3.02[EMC_D2]    IO6
P3.03[EMC_D3]    IO14
P3.04[EMC_D4]    IO13
P3.05[EMC_D5]    IO12
P3.06[EMC_D6]    IO10
P3.07[EMC_D7]    IO9
P3.08[EMC_D8]    IO0
P3.09[EMC_D9]    IO2
P3.10[EMC_D10]   IO5
P3.11[EMC_D11]   IO1
P3.12[EMC_D12]   IO15
P3.13[EMC_D13]   IO7
P3.14[EMC_D14]   IO11
P3.15[EMC_D15]   IO8

P4.00[EMC_A0]    A11
P4.01[EMC_A1]    A13
P4.02[EMC_A2]    A10
P4.03[EMC_A3]    A12
P4.04[EMC_A4]    A9
P4.05[EMC_A5]    A8
P4.06[EMC_A6]    A15
P4.07[EMC_A7]    A14
P4.08[EMC_A8]    A7
P4.09[EMC_A9]    A6
P4.10[EMC_A10]   A5
P4.11[EMC_A11]   A3
P4.12[EMC_A12]   A0
P4.13[EMC_A13]   A1
P4.14[EMC_A14]   A4
P4.15[EMC_A15]   A2
P4.16[EMC_A16]   A16
P4.17[EMC_A17]   A17
P4.24[EMC_OE]    OE
P4.25[EMC_WE]    WE
P4.26[EMC_BLS0]  LB
P4.27[EMC_BLS1]  UB
P4.30[EMC_CS0]   CS1

The scrambled order of (lower) address (A0..A15) and data (D0..D15) connections simplifies the routing and should(?) not matter.

The following code initializes the EMC:

PCONP |= 1<<11/*PCEMC*/;

IOCON_P3_00 = 1<<0/*EMC_D[0]*/ | 1<<5/*HYS*/;
IOCON_P3_01 = 1<<0/*EMC_D[1]*/ | 1<<5/*HYS*/;
IOCON_P3_02 = 1<<0/*EMC_D[2]*/ | 1<<5/*HYS*/;
IOCON_P3_03 = 1<<0/*EMC_D[3]*/ | 1<<5/*HYS*/;
IOCON_P3_04 = 1<<0/*EMC_D[4]*/ | 1<<5/*HYS*/;
IOCON_P3_05 = 1<<0/*EMC_D[5]*/ | 1<<5/*HYS*/;
IOCON_P3_06 = 1<<0/*EMC_D[6]*/ | 1<<5/*HYS*/;
IOCON_P3_07 = 1<<0/*EMC_D[7]*/ | 1<<5/*HYS*/;
IOCON_P3_08 = 1<<0/*EMC_D[8]*/ | 1<<5/*HYS*/;
IOCON_P3_09 = 1<<0/*EMC_D[9]*/ | 1<<5/*HYS*/;
IOCON_P3_10 = 1<<0/*EMC_D[10]*/ | 1<<5/*HYS*/;
IOCON_P3_11 = 1<<0/*EMC_D[11]*/ | 1<<5/*HYS*/;
IOCON_P3_12 = 1<<0/*EMC_D[12]*/ | 1<<5/*HYS*/;
IOCON_P3_13 = 1<<0/*EMC_D[13]*/ | 1<<5/*HYS*/;
IOCON_P3_14 = 1<<0/*EMC_D[14]*/ | 1<<5/*HYS*/;
IOCON_P3_15 = 1<<0/*EMC_D[15]*/ | 1<<5/*HYS*/;

IOCON_P4_00 = 1<<0/*EMC_A[0]*/ | 1<<5/*HYS*/;
IOCON_P4_01 = 1<<0/*EMC_A[1]*/ | 1<<5/*HYS*/;
IOCON_P4_02 = 1<<0/*EMC_A[2]*/ | 1<<5/*HYS*/;
IOCON_P4_03 = 1<<0/*EMC_A[3]*/ | 1<<5/*HYS*/;
IOCON_P4_04 = 1<<0/*EMC_A[4]*/ | 1<<5/*HYS*/;
IOCON_P4_05 = 1<<0/*EMC_A[5]*/ | 1<<5/*HYS*/;
IOCON_P4_06 = 1<<0/*EMC_A[6]*/ | 1<<5/*HYS*/;
IOCON_P4_07 = 1<<0/*EMC_A[7]*/ | 1<<5/*HYS*/;
IOCON_P4_08 = 1<<0/*EMC_A[8]*/ | 1<<5/*HYS*/;
IOCON_P4_09 = 1<<0/*EMC_A[9]*/ | 1<<5/*HYS*/;
IOCON_P4_10 = 1<<0/*EMC_A[10]*/ | 1<<5/*HYS*/;
IOCON_P4_11 = 1<<0/*EMC_A[11]*/ | 1<<5/*HYS*/;
IOCON_P4_12 = 1<<0/*EMC_A[12]*/ | 1<<5/*HYS*/;
IOCON_P4_13 = 1<<0/*EMC_A[13]*/ | 1<<5/*HYS*/;
IOCON_P4_14 = 1<<0/*EMC_A[14]*/ | 1<<5/*HYS*/;
IOCON_P4_15 = 1<<0/*EMC_A[15]*/ | 1<<5/*HYS*/;
IOCON_P4_16 = 1<<0/*EMC_A[16]*/ | 1<<5/*HYS*/;
IOCON_P4_17 = 1<<0/*EMC_A[17]*/ | 1<<5/*HYS*/;
IOCON_P4_24 = 1<<0/*EMC_OE*/ | 1<<5/*HYS*/;
IOCON_P4_25 = 1<<0/*EMC_WE*/ | 1<<5/*HYS*/;
IOCON_P4_26 = 1<<0/*EMC_BLS0*/ | 1<<5/*HYS*/;
IOCON_P4_27 = 1<<0/*EMC_BLS1*/ | 1<<5/*HYS*/;
IOCON_P4_30 = 1<<0/*EMC_CS*/ | 1<<5/*HYS*/;

EMCControl = 0;

SCS &= ~(1<<0/*EMCSC*/);
EMCCLKSEL = 1;// CCLK=120MHz

EMCConfig = 0;
EMCStaticConfig0 = 1<<0/*MW*/ | 1<<7/*PB*/;
EMCStaticWaitWen0 = 0;// 10ns
EMCStaticWaitOen0 = 0;// 10ns
EMCStaticWaitRd0 = 3;// 55ns
EMCStaticWaitWr0 = 2;// 55ns

EMCControl = 1<<0/*E*/;

Any ideas about what's wrong?

Thanks in advance.

Re: LPC1778 - problems with SRAM byte read access

lpcware — Wed, 15 Jun 2016 17:47:47 GMT

Content originally posted in LPCWare by rda on Fri Mar 27 03:05:43 MST 2015
Forget about the fact that the first read access succeeds - when using volatile pointers BYTE (8-bit) access fails immediately.
Could the problem be related to the scrambled address lines in combination with the address shift feature?

topic Re: LPC1778 - problems with SRAM byte read access in LPC Microcontrollers

LPC1778 - problems with SRAM byte read access

Re: LPC1778 - problems with SRAM byte read access