LPC MicrocontrollersのトピックRe: Interval of RIT (Repetitive Interrupt Timer) SDK example

Interval of RIT (Repetitive Interrupt Timer) SDK example

yasokada — Wed, 09 Oct 2019 00:33:52 GMT

My Environment:

- OS: Ubuntu 18.04 LTS

- Board: LPCXpresso54628

- IDE: MCUXpresso IDE v11.0.1 [Build 2563] [2019-09-01]

I examined rit.c from SDK example. With the code, I confirmed that the LED is toggled in one second interval.

However, I cannot understand how the one second interval is configured.

Related sentences in [rit.c] may be

A. #define RIT_SOURCE_CLOCK CLOCK_GetFreq(kCLOCK_CoreSysClk)

B. CLOCK_EnableClock(kCLOCK_Gpio3);

C. RIT_SetTimerCompare(RIT, RIT_SOURCE_CLOCK);

----

Q1. What is the kCLOCK_Gpio3 (and others, such as kCLOCK_Gpio0)? I found no explanations on documents.

Q2. Why is kCLOCK_Gpio3 used in this example? (Related to kCLOCK_CoreSysClk?)

Q3. How do they produce one second interval?

----

Thanks in advance.

Re: Interval of RIT (Repetitive Interrupt Timer) SDK example

Alice_Yang — Thu, 10 Oct 2019 08:14:34 GMT

Hello Yas Okada ,

Q1. What is the kCLOCK_Gpio3 (and others, such as kCLOCK_Gpio0)? I found no explanations on documents.

-> These are Clock gate names used for CLOCK_EnableClock/CLOCK_DisableClock.

kCLOCK_Gpio3 stand for GPIO3 (17). You can have a look the register of "AHB Clock Control register" in UM.

Q2. Why is kCLOCK_Gpio3 used in this example? (Related to kCLOCK_CoreSysClk?)

-> Because the LED function used the port3_14, need enable the clock of GPIO3.

/* Init LED. */
LED_INIT();

Q3. How do they produce one second interval?

-> Have a look at

/* Init rit module */
RIT_Init(RIT, &ritConfig);

and related register.

Have a great day,
TIC

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Re: Interval of RIT (Repetitive Interrupt Timer) SDK example

yasokada — Thu, 10 Oct 2019 23:44:51 GMT

Thank you very much for your answer.

About Q1 and Q2, I understand that. I will read related documents (although I have no idea which documents is appropriate to read).

About Q3, I will read the document again. (I read once, but it is not clear how to make "one second interval").

PS.

In my opinion, LPC provides various documents detailed written, but no good document for the beginners, such as QuickStart Guide". That's why I have difficulty in studying LPC MCU after studying several MCUs such as MSP430, STM32 and others.

Re: Interval of RIT (Repetitive Interrupt Timer) SDK example

yasokada — Fri, 11 Oct 2019 03:33:22 GMT

For readers of this topic, I leave information on the documents to read.

In UM11305.pdf (Rev 2.1) page 10, I found

> User LEDs

> P2-2 (D9), P3-3 (D11), and P3-14 (D12)

I understand that D12 uses P3-14.

Re: Interval of RIT (Repetitive Interrupt Timer) SDK example

Alice_Yang — Fri, 11 Oct 2019 08:26:04 GMT

Hello OKada,

You can find the Datasheet , User manual of this chip , the board user manual and also some other Application note

from: LPC546XX Microcontroller (MCU) Family | NXP

Have a great day,
TIC

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Re: Interval of RIT (Repetitive Interrupt Timer) SDK example

yasokada — Sat, 12 Oct 2019 01:26:03 GMT

I understand how to set the timer interval.

In rit.c, 1Hz interval is defined as

```

#define RIT_SOURCE_CLOCK CLOCK_GetFreq(kCLOCK_CoreSysClk)

...

/* Set timer period for Compare register. */
RIT_SetTimerCompare(RIT, RIT_SOURCE_CLOCK);

```

The function RIT_SetTimerCompare() is defined in drivers/fsl_rit.c. That will set the timer counter.

If we want to set the interval to 1/2Hz, we write

```

/* Set timer period for Compare register. */
RIT_SetTimerCompare(RIT, RIT_SOURCE_CLOCK / 2);

```

Similarly, to 2Hz,

```

/* Set timer period for Compare register. */
RIT_SetTimerCompare(RIT, RIT_SOURCE_CLOCK * 2);

```

Re: Interval of RIT (Repetitive Interrupt Timer) SDK example

yasokada — Sat, 12 Oct 2019 02:28:39 GMT

> Q2. Why is kCLOCK_Gpio3 used in this example? (Related to kCLOCK_CoreSysClk?)

I found the description on the document.

UM10912 Rev 1.8 - 28 April 2017
Chapter 11: LPC546xx General Purpose I/O (GPIO)
11.3 Basic configuration

> For the GPIO port registers, enable the clock to each GPIO port in the AHBCLKCTRL0 register (Table 137).