LPC Microcontrollers中的主题 Re: problem with EMC LPC1788

problem with EMC LPC1788

lpcware — Wed, 15 Jun 2016 17:44:46 GMT

Content originally posted in LPCWare by kickoune on Fri Dec 16 02:36:44 MST 2011
hello, i have reading lot of topic about configuration of EMC.I have change micro on my projet board ( LPC2478 --> LPC1788).
I have try to translate startup.s to C file for initialisation of EMC. i havec add EMCDELAYCTRL = 0 (no present at LPC2478)
i use AM29F320DT x2 for flash (const of picture for lcd) and MT48LC4M32B2 for SDRAM.

i think SRAM works because, variable is defined in external RAM. But external flash not works. 0xFFFF in const variable declared external ROM.

my initialisation in system_Init()

void SystemInit (void)
{
volatile uint32_t temp;
//volatile uint32_t* Pt;
uint32_t l_i;
//static uint32_t i = 0;

#if (CLOCK_SETUP)                       /* Clock Setup                        */
  LPC_SC->SCS       = SCS_Val;
  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
  }

  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/

#if (PLL0_SETUP)
  LPC_SC->PLL0CFG   = PLL0CFG_Val;
  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
  LPC_SC->PLL0FEED  = 0xAA;
  LPC_SC->PLL0FEED  = 0x55;
  while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0                    */
#endif

#if (PLL1_SETUP)
  LPC_SC->PLL1CFG   = PLL1CFG_Val;
  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
  LPC_SC->PLL1FEED  = 0xAA;
  LPC_SC->PLL1FEED  = 0x55;
  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
#endif

  LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */
  LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */
  LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */
  LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */
  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
#endif

#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
  LPC_SC->FLASHCFG  = FLASHCFG_Val|0x03A;
#endif
#ifdef  __RAM_MODE__
  SCB->VTOR  = 0x10000000 & 0x3FFFFF80;
#else
  SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
#endif

SystemCoreClockUpdate();


//PINSEL 0
LPC_IOCON->P0_00 = 0xB1;
LPC_IOCON->P0_01 = 0xB1;
LPC_IOCON->P0_02 = 0xB1;
LPC_IOCON->P0_03 = 0xB1;
LPC_IOCON->P0_04 = 0xB1;
LPC_IOCON->P0_05 = 0xB0;
LPC_IOCON->P0_06 = 0xB1;
LPC_IOCON->P0_07 = 0xA1;
LPC_IOCON->P0_08 = 0xA1;
LPC_IOCON->P0_09 = 0xA1;
LPC_IOCON->P0_10 = 0xB0;
LPC_IOCON->P0_11 = 0xB0;
LPC_IOCON->P0_12 = 0xB0;
LPC_IOCON->P0_13 = 0xB0;
LPC_IOCON->P0_14 = 0xB0;
LPC_IOCON->P0_15 = 0xB2;
LPC_IOCON->P0_16 = 0xB0;
LPC_IOCON->P0_17 = 0xB2;
LPC_IOCON->P0_18 = 0xB2;
LPC_IOCON->P0_19 = 0xB0;
LPC_IOCON->P0_20 = 0xB0;
LPC_IOCON->P0_21 = 0xB0;
LPC_IOCON->P0_22 = 0xB0;
LPC_IOCON->P0_23 = 0xB0;
LPC_IOCON->P0_24 = 0xB0;
LPC_IOCON->P0_25 = 0xB0;
LPC_IOCON->P0_26 = 0xB0;
LPC_IOCON->P0_27 = 0xB0;
LPC_IOCON->P0_28 = 0xB0;
LPC_IOCON->P0_29 = 0xB1;
LPC_IOCON->P0_30 = 0xB1;
LPC_IOCON->P0_31 = 0xB0;

//PINSEL 1
LPC_IOCON->P1_00 = 0xB0;
LPC_IOCON->P1_01 = 0xB0;
LPC_IOCON->P1_02 = 0xB0;
LPC_IOCON->P1_03 = 0xB0;
LPC_IOCON->P1_04 = 0xB0;
LPC_IOCON->P1_05 = 0xB0;
LPC_IOCON->P1_06 = 0xB0;
LPC_IOCON->P1_07 = 0xB0;
LPC_IOCON->P1_08 = 0xB0;
LPC_IOCON->P1_09 = 0xB0;
LPC_IOCON->P1_10 = 0xB0;
LPC_IOCON->P1_11 = 0xB0;
LPC_IOCON->P1_12 = 0xB0;
LPC_IOCON->P1_13 = 0xB0;
LPC_IOCON->P1_14 = 0xB0;
LPC_IOCON->P1_15 = 0xB0;
LPC_IOCON->P1_16 = 0xB0;
LPC_IOCON->P1_17 = 0xB0;
LPC_IOCON->P1_18 = 0xB2;
LPC_IOCON->P1_19 = 0xB1;
LPC_IOCON->P1_20 = 0xB1;
LPC_IOCON->P1_21 = 0xB1;
LPC_IOCON->P1_22 = 0xB1;
LPC_IOCON->P1_23 = 0xB1;
LPC_IOCON->P1_24 = 0xB1;
LPC_IOCON->P1_25 = 0xB1;
LPC_IOCON->P1_26 = 0xB1;
LPC_IOCON->P1_27 = 0xB1;
LPC_IOCON->P1_28 = 0xB1;
LPC_IOCON->P1_29 = 0xB1;
LPC_IOCON->P1_30 = 0xB2;
LPC_IOCON->P1_31 = 0xA8;

//PINSEL 2
LPC_IOCON->P2_00 = 0xB0;
LPC_IOCON->P2_01 = 0xB0;
LPC_IOCON->P2_02 = 0xB0;
LPC_IOCON->P2_03 = 0xB0;
LPC_IOCON->P2_04 = 0xB0;
LPC_IOCON->P2_05 = 0xB0;
LPC_IOCON->P2_06 = 0xB0;
LPC_IOCON->P2_07 = 0xB0;
LPC_IOCON->P2_08 = 0xB0;
LPC_IOCON->P2_09 = 0xB0;
LPC_IOCON->P2_10 = 0xB0;
LPC_IOCON->P2_11 = 0xB1;
LPC_IOCON->P2_12 = 0xB1;
LPC_IOCON->P2_13 = 0xB1;
LPC_IOCON->P2_14 = 0xB0;
LPC_IOCON->P2_15 = 0xB0;
LPC_IOCON->P2_16 = 0xB1;
LPC_IOCON->P2_17 = 0xB1;
LPC_IOCON->P2_18 = 0xB1;
LPC_IOCON->P2_19 = 0xB0;
LPC_IOCON->P2_20 = 0xB1;
LPC_IOCON->P2_21 = 0xB0;
LPC_IOCON->P2_22 = 0xB0;
LPC_IOCON->P2_23 = 0xB0;
LPC_IOCON->P2_24 = 0xB1;
LPC_IOCON->P2_25 = 0xB0;
LPC_IOCON->P2_26 = 0xB0;
LPC_IOCON->P2_27 = 0xB0;
LPC_IOCON->P2_28 = 0xB1;
LPC_IOCON->P2_29 = 0xB1;
LPC_IOCON->P2_30 = 0xB1;
LPC_IOCON->P2_31 = 0xB1;

//PINSEL 3
LPC_IOCON->P3_00 = 0xB1;
LPC_IOCON->P3_01 = 0xB1;
LPC_IOCON->P3_02 = 0xB1;
LPC_IOCON->P3_03 = 0xB1;
LPC_IOCON->P3_04 = 0xB1;
LPC_IOCON->P3_05 = 0xB1;
LPC_IOCON->P3_06 = 0xB1;
LPC_IOCON->P3_07 = 0xB1;
LPC_IOCON->P3_08 = 0xB1;
LPC_IOCON->P3_09 = 0xB1;
LPC_IOCON->P3_10 = 0xB1;
LPC_IOCON->P3_11 = 0xB1;
LPC_IOCON->P3_12 = 0xB1;
LPC_IOCON->P3_13 = 0xB1;
LPC_IOCON->P3_14 = 0xB1;
LPC_IOCON->P3_15 = 0xB1;
LPC_IOCON->P3_16 = 0xB1;
LPC_IOCON->P3_17 = 0xB1;
LPC_IOCON->P3_18 = 0xB1;
LPC_IOCON->P3_19 = 0xB1;
LPC_IOCON->P3_20 = 0xB1;
LPC_IOCON->P3_21 = 0xB1;
LPC_IOCON->P3_22 = 0xB1;
LPC_IOCON->P3_23 = 0xB1;
LPC_IOCON->P3_24 = 0xB1;
LPC_IOCON->P3_25 = 0xB1;
LPC_IOCON->P3_26 = 0xB1;
LPC_IOCON->P3_27 = 0xB1;
LPC_IOCON->P3_28 = 0xB1;
LPC_IOCON->P3_29 = 0xB1;
LPC_IOCON->P3_30 = 0xB1;
LPC_IOCON->P3_31 = 0xB1;

//PINSEL 4
LPC_IOCON->P4_00 = 0xB1;
LPC_IOCON->P4_01 = 0xB1;
LPC_IOCON->P4_02 = 0xB1;
LPC_IOCON->P4_03 = 0xB1;
LPC_IOCON->P4_04 = 0xB1;
LPC_IOCON->P4_05 = 0xB1;
LPC_IOCON->P4_06 = 0xB1;
LPC_IOCON->P4_07 = 0xB1;
LPC_IOCON->P4_08 = 0xB1;
LPC_IOCON->P4_09 = 0xB1;
LPC_IOCON->P4_10 = 0xB1;
LPC_IOCON->P4_11 = 0xB1;
LPC_IOCON->P4_12 = 0xB1;
LPC_IOCON->P4_13 = 0xB1;
LPC_IOCON->P4_14 = 0xB1;
LPC_IOCON->P4_15 = 0xB1;
LPC_IOCON->P4_16 = 0xB1;
LPC_IOCON->P4_17 = 0xB1;
LPC_IOCON->P4_18 = 0xB1;
LPC_IOCON->P4_19 = 0xB1;
LPC_IOCON->P4_20 = 0xB1;
LPC_IOCON->P4_21 = 0xB1;
LPC_IOCON->P4_22 = 0xB1;
LPC_IOCON->P4_23 = 0xB1;
LPC_IOCON->P4_24 = 0xB1;
LPC_IOCON->P4_25 = 0xB1;
LPC_IOCON->P4_26 = 0xB1;
LPC_IOCON->P4_27 = 0xB1;
LPC_IOCON->P4_28 = 0xB3;
LPC_IOCON->P4_29 = 0xB3;
LPC_IOCON->P4_30 = 0xB1;
LPC_IOCON->P4_31 = 0xB1;


LPC_SC->EMCDLYCTL = 0;

//PCONP DEJA ALIMENTEE
//CLOCK CONFIGURE CCLK 72MHZ
LPC_EMC->Control = EMC_CTRL_Val;               //enabled
LPC_EMC->Config = EMC_CONFIG_Val;                //little endian CLK:CLKOUT ratio 1:1
//PIN CONFIGURE AU DESSUS

LPC_EMC->DynamicRP = EMC_DYN_RP_Val;        //0
LPC_EMC->DynamicRAS = EMC_DYN_RAS_Val;      //2
LPC_EMC->DynamicSREX = EMC_DYN_SREX_Val;    //5
LPC_EMC->DynamicAPR = EMC_DYN_APR_Val;      //1
LPC_EMC->DynamicDAL = EMC_DYN_DAL_Val;      //4
LPC_EMC->DynamicWR = EMC_DYN_WR_Val;        //0
LPC_EMC->DynamicRC = EMC_DYN_RC_Val;        //4
LPC_EMC->DynamicRFC = EMC_DYN_RFC_Val;      //4
LPC_EMC->DynamicXSR = EMC_DYN_XSR_Val;      //5
LPC_EMC->DynamicRRD = EMC_DYN_RRD_Val;      //0
LPC_EMC->DynamicMRD = EMC_DYN_MRD_Val;      //0

LPC_EMC->DynamicReadConfig = EMC_DYN_RD_CFG_Val;            //1
LPC_EMC->DynamicRasCas0 = EMC_DYN_RASCAS0_Val;              //0x0202
LPC_EMC->DynamicConfig0 = EMC_DYN_CFG0_Val & ~((uint32_t)BUFEN_Const);        //b19 = 0

for (l_i=1440000;l_i>0;l_i--);   //attente environ 100ms


LPC_EMC->DynamicControl = NOP_CMD | 0x03;                           //write NOP COMMAND (3 << 7)
for (l_i=2880000;l_i>0;l_i--);   //attente environ 200ms


LPC_EMC->DynamicControl = PALL_CMD | 0x03;                           //precharge all command   (2 << 7)
LPC_EMC->DynamicRefresh = 2;

for (l_i=64;l_i>0;l_i--);   //attente
LPC_EMC->DynamicRefresh = EMC_DYN_RFSH_Val;                         //0x7FF


LPC_EMC->DynamicControl = MODE_CMD | 0x03;                           //write MODE COMMAND     (1 << 7)

temp =*((uint32_t*) (DYN_MEM0_BASE + (((uint32_t)0x11) << 11)));

LPC_EMC->DynamicControl = NORMAL_CMD;                           //write NORMAL COMMAND        (0 << 7)

#if (EMC_DYN_CFG0_Val & BUFEN_Const)
LPC_EMC->DynamicConfig0 = EMC_DYN_CFG0_Val;                   //0x85508
#endif

for (l_i=14400;l_i>0;l_i--);     //attente
for (l_i=1440000;l_i>0;l_i--);   //attente

//FLASH EXTERNE
LPC_EMC->StaticConfig0   = EMC_STA_CFG0_Val;      //EMC STATIC COnfig0      82
LPC_EMC->StaticWaitWen0  = EMC_STA_WWEN0_Val;     //0
LPC_EMC->StaticWaitOen0  = EMC_STA_WOEN0_Val;     //0
LPC_EMC->StaticWaitRd0   = EMC_STA_WRD0_Val;      //4
LPC_EMC->StaticWaitPage0 = EMC_STA_WPAGE0_Val;    //0
LPC_EMC->StaticWaitWr0   = EMC_STA_WWR0_Val;      //5
LPC_EMC->StaticWaitTurn0 = EMC_STA_WTURN0_Val;    //0

for (l_i=144000;l_i>0;l_i--);   //attente


temp = *(uint32_t*) (LPC_EMC_BASE + EMC_STA_EXT_W_OFS);             //0FFSET 0x880
[\code]
INI FILE Utilities

/******************************************************************************/
/* Ext_NOR.INI: External NOR Flash Initialization File for NXP LPC24xx        */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>                           // 
/******************************************************************************/
/* This file is part of the uVision/ARM development tools.                    */
/* Copyright (c) 2005-2007 Keil Software. All rights reserved.                */
/* This software may only be used under the terms of a valid, current,        */
/* end user licence from KEIL for a compatible version of KEIL software       */
/* development tools. Nothing else gives you the right to use this software.  */
/******************************************************************************/

_WDWORD(0x2009C000, 0x00000001);        // EMC_CTRL: Disable address mirror

_WDWORD(0x2009C008, 0x00000000);        //EMCCONFIG: rajout tr
_WDWORD(0x400FC1DC, 0x00000000);        //EMCDLYCTL: TR

_WDWORD(0x400FC0C4, 0x00000800);        // PCONP: Turn on EMC PCLK

_WDWORD(0x4002C140, 0x000000B1);        //P2.16       CAS
_WDWORD(0x4002C144, 0x000000B1);        //P2.17       RAS
_WDWORD(0x4002C148, 0x000000B1);        //P2.18       CLKOUt0
_WDWORD(0x4002C150, 0x000000B1);        //P2.20       DYCS0
_WDWORD(0x4002C160, 0x000000B1);        //P2.24       CKEOUT0
_WDWORD(0x4002C170, 0x000000B1);        //P2.28       DQMOUT0
_WDWORD(0x4002C174, 0x000000B1);        //P2.29       DQMOUT1
_WDWORD(0x4002C178, 0x000000B1);        //P2.30       DQMOUT2

_WDWORD(0x4002C180, 0x000000B1);        //P3.00       D0
_WDWORD(0x4002C184, 0x000000B1);        //P3.01       D1
_WDWORD(0x4002C188, 0x000000B1);        //P3.02       D2
_WDWORD(0x4002C18C, 0x000000B1);        //P3.03       D3
_WDWORD(0x4002C190, 0x000000B1);        //P3.04       D4
_WDWORD(0x4002C194, 0x000000B1);        //P3.05       D5
_WDWORD(0x4002C198, 0x000000B1);        //P3.06       D6
_WDWORD(0x4002C19C, 0x000000B1);        //P3.07       D7
_WDWORD(0x4002C1A0, 0x000000B1);        //P3.08       D8
_WDWORD(0x4002C1A4, 0x000000B1);        //P3.09       D9

_WDWORD(0x4002C200, 0x000000B1);        //P4.00       A0
_WDWORD(0x4002C204, 0x000000B1);        //P4.01       A1
_WDWORD(0x4002C208, 0x000000B1);        //P4.02       A2
_WDWORD(0x4002C20C, 0x000000B1);        //P4.03       A3
_WDWORD(0x4002C210, 0x000000B1);        //P4.04       A4
_WDWORD(0x4002C214, 0x000000B1);        //P4.05       A5
_WDWORD(0x4002C218, 0x000000B1);        //P4.06       A6
_WDWORD(0x4002C21C, 0x000000B1);        //P4.07       A7
_WDWORD(0x4002C220, 0x000000B1);        //P4.08       A8
_WDWORD(0x4002C224, 0x000000B1);        //P4.09       A9
_WDWORD(0x4002C228, 0x000000B1);        //P4.10       A10
_WDWORD(0x4002C22C, 0x000000B1);        //P4.11       A11
_WDWORD(0x4002C230, 0x000000B1);        //P4.12       A12
_WDWORD(0x4002C234, 0x000000B1);        //P4.13       A13
_WDWORD(0x4002C238, 0x000000B1);        //P4.14       A14
_WDWORD(0x4002C23C, 0x000000B1);        //P4.15       A15
_WDWORD(0x4002C240, 0x000000B1);        //P4.16       A16
_WDWORD(0x4002C244, 0x000000B1);        //P4.17       A17
_WDWORD(0x4002C248, 0x000000B1);        //P4.18       A18
_WDWORD(0x4002C24C, 0x000000B1);        //P4.19       A19
_WDWORD(0x4002C250, 0x000000B1);        //P4.20       A20
_WDWORD(0x4002C254, 0x000000B1);        //P4.21       A21
_WDWORD(0x4002C258, 0x000000B1);        //P4.22       A22
_WDWORD(0x4002C25C, 0x000000B1);        //P4.23       A23
_WDWORD(0x4002C260, 0x000000B1);        //P4.24       OE
_WDWORD(0x4002C264, 0x000000B1);        //P4.25       WE
_WDWORD(0x4002C268, 0x000000B1);        //P4.26       BLS0
_WDWORD(0x4002C26C, 0x000000B1);        //P4.27       BLS1

_WDWORD(0x4002C278, 0x000000B1);        //P4.30       CS0
_WDWORD(0x4002C27C, 0x000000B1);        //P4.31       CS1


// Setup controller for External NOR Flash 
_WDWORD(0x2009C200, 0x00000082);        // EMCStaticConfig0
_WDWORD(0x2009C204, 0x00000000);        // EMCStaticWaitWen0 0x2 EA / 0 x292
_WDWORD(0x2009C208, 0x00000000);        // EMCStaticWaitOen0 0x2 EA / 0 x292
_WDWORD(0x2009C20C, 0x00000004);        // EMCStaticWaitRd0  0x5 EA / 4 x292
_WDWORD(0x2009C210, 0x00000000);        // EMCStaticWaitPage0
_WDWORD(0x2009C214, 0x00000005);        // EMCStaticWaitWr0
_WDWORD(0x2009C218, 0x00000000);        // EMCStaticWaitTurn0

[\CODE]


have you an idea?
have you a similar INI?


thank's

Re: problem with EMC LPC1788

lpcware — Wed, 15 Jun 2016 17:44:47 GMT

Content originally posted in LPCWare by Marc Crandall on Mon Dec 19 14:54:16 MST 2011
I configure a NOR and an SDRAM device. (SST38VF640 and MT48LC16M16)

This is my working INI:

<code>

DEFINE INT SDRAM_BASE_ADDR;
DEFINE INT EMC_BASE;      // EMC Base Address
DEFINE INT EMC_CTRL_REG;
DEFINE INT EMC_STAT_REG;
DEFINE INT EMC_CONFIG_REG;
DEFINE INT EMC_DYN_CTRL_REG;
DEFINE INT EMC_DYN_RFSH_REG;
DEFINE INT EMC_DYN_RD_CFG_REG;
DEFINE INT EMC_DYN_RP_REG;
DEFINE INT EMC_DYN_RAS_REG;
DEFINE INT EMC_DYN_SREX_REG;
DEFINE INT EMC_DYN_APR_REG;
DEFINE INT EMC_DYN_DAL_REG;
DEFINE INT EMC_DYN_WR_REG;
DEFINE INT EMC_DYN_RC_REG;
DEFINE INT EMC_DYN_RFC_REG;
DEFINE INT EMC_DYN_XSR_REG;
DEFINE INT EMC_DYN_RRD_REG;
DEFINE INT EMC_DYN_MRD_REG;
DEFINE INT EMC_DYN_CFG0_REG;
DEFINE INT EMC_DYN_RASCAS0_REG;
//note: missing the other dyn mem register offsets.
DEFINE INT EMC_STA_CFG0_REG;
DEFINE INT EMC_STA_WWEN0_REG;
DEFINE INT EMC_STA_WOEN0_REG;
DEFINE INT EMC_STA_WRD0_REG;
DEFINE INT EMC_STA_WPAGE0_REG;
DEFINE INT EMC_STA_WWR0_REG;
DEFINE INT EMC_STA_WTURN0_REG;
//note: missing the other static mem register offsets.
DEFINE INT EMC_STA_EXT_W_REG;
DEFINE INT PCONP_REG;
DEFINE INT EMCDLYCTL_REG;
DEFINE INT EMCCAL_REG;
DEFINE INT EMCClock_m
DEFINE INT SCS_REG;

SDRAM_BASE_ADDR = 0xA0000000;
EMC_BASE = 0x2009C000;    // EMC Base Address
EMC_CTRL_REG = EMC_BASE + 0x000;
EMC_STAT_REG = EMC_BASE + 0x004;
EMC_CONFIG_REG = EMC_BASE + 0x008;
EMC_DYN_CTRL_REG = EMC_BASE + 0x020;
EMC_DYN_RFSH_REG = EMC_BASE + 0x024;
EMC_DYN_RD_CFG_REG = EMC_BASE + 0x028;
EMC_DYN_RP_REG = EMC_BASE + 0x030;
EMC_DYN_RAS_REG = EMC_BASE + 0x034;
EMC_DYN_SREX_REG = EMC_BASE + 0x038;
EMC_DYN_APR_REG = EMC_BASE + 0x03C;
EMC_DYN_DAL_REG = EMC_BASE + 0x040;
EMC_DYN_WR_REG = EMC_BASE + 0x044;
EMC_DYN_RC_REG = EMC_BASE + 0x048;
EMC_DYN_RFC_REG = EMC_BASE + 0x04C;
EMC_DYN_XSR_REG = EMC_BASE + 0x050;
EMC_DYN_RRD_REG = EMC_BASE + 0x054;
EMC_DYN_MRD_REG = EMC_BASE + 0x058;
EMC_DYN_CFG0_REG = EMC_BASE + 0x100;
EMC_DYN_RASCAS0_REG = EMC_BASE + 0x104;
EMC_STA_CFG0_REG = EMC_BASE + 0x200;
EMC_STA_WWEN0_REG = EMC_BASE + 0x204;
EMC_STA_WOEN0_REG = EMC_BASE + 0x208;
EMC_STA_WRD0_REG = EMC_BASE + 0x20C;
EMC_STA_WPAGE0_REG = EMC_BASE + 0x210;
EMC_STA_WWR0_REG = EMC_BASE + 0x214;
EMC_STA_WTURN0_REG = EMC_BASE + 0x218;
EMC_STA_EXT_W_REG = EMC_BASE + 0x080;
PCONP_REG = 0x400FC0C4;
EMCDLYCTL_REG = 0x400FC1DC;
EMCCAL_REG = 0x400FC1E0;
EMCClock_m = 78000000;
SCS_REG = 0x400FC1A0;

FUNC int NS_2_CLKS(int ns)
{
    double tCLK_ns;
    tCLK_ns = ((double)EMCClock_m / 1000000000.0 );    // CCLK period in ns
    return (int)((double)(ns) * tCLK_ns );          // convert ns to CCLKs
}

FUNC void Setup (void)
{

    printf("START - Setup() \r\n");

    SP = _RDWORD(0x00040000);           // Setup Stack Pointer
    PC = _RDWORD(0x00040004);           // Setup Program Counter
    _WDWORD(0xE000ED08, 0x00040000);    // Setup Vector Table Offset Register

    //SP = _RDWORD(0x00000000);           // Setup Stack Pointer
    //PC = _RDWORD(0x00000004);           // Setup Program Counter
    //_WDWORD(0xE000ED08, 0x00000000);    // Setup Vector Table Offset Register

    printf("END - Setup() \r\n");
}

FUNC void init_emc(void)
{
    //*********************************************
    // PIN CONFIGURATION
    //*********************************************
    _WDWORD(0x4002C140, _RDWORD(0x4002C140) | 0x1);           //LPC_IOCON->P2_16 |= 1;              // CASN @ P2.16         (SDRAM Column Address Strobe)
    _WDWORD(0x4002C144, _RDWORD(0x4002C144) | 0x1);           //LPC_IOCON->P2_17 |= 1;              // RASN @ P2.17         (SDRAM Row Address Strobe)
    _WDWORD(0x4002C148, _RDWORD(0x4002C148) | 0x1);           //LPC_IOCON->P2_18 |= 1;              // CLK[0] @ P2.18       (SDRAM System Clock)
    _WDWORD(0x4002C150, _RDWORD(0x4002C150) | 0x1);           //LPC_IOCON->P2_20 |= 1;              // DYCSN[0] @ P2.20     (SDRAM Chip Select)
    _WDWORD(0x4002C160, _RDWORD(0x4002C160) | 0x1);           //LPC_IOCON->P2_24 |= 1;              // CKE[0] @ P2.24       (SDRAM Clock Enable)
    _WDWORD(0x4002C170, _RDWORD(0x4002C170) | 0x1);           //LPC_IOCON->P2_28 |= 1;              // DQM[0] @ P2.28       (SDRAM Data Input/Output Mask)
    _WDWORD(0x4002C174, _RDWORD(0x4002C174) | 0x1);           //LPC_IOCON->P2_29 |= 1;              // DQM[1] @ P2.29       (SDRAM Data Input/Output Mask)

    _WDWORD(0x4002C180, _RDWORD(0x4002C180) | 0x1);           // LPC_IOCON->P3_0 |= 1; /* D0 @ P3.0 */
    _WDWORD(0x4002C184, _RDWORD(0x4002C184) | 0x1);           // LPC_IOCON->P3_1 |= 1; /* D1 @ P3.1 */
    _WDWORD(0x4002C188, _RDWORD(0x4002C188) | 0x1);           // LPC_IOCON->P3_2 |= 1; /* D2 @ P3.2 */
    _WDWORD(0x4002C18C, _RDWORD(0x4002C18C) | 0x1);           // LPC_IOCON->P3_3 |= 1; /* D3 @ P3.3 */
    _WDWORD(0x4002C190, _RDWORD(0x4002C190) | 0x1);           // LPC_IOCON->P3_4 |= 1; /* D4 @ P3.4 */
    _WDWORD(0x4002C194, _RDWORD(0x4002C194) | 0x1);           // LPC_IOCON->P3_5 |= 1; /* D5 @ P3.5 */
    _WDWORD(0x4002C198, _RDWORD(0x4002C198) | 0x1);           // LPC_IOCON->P3_6 |= 1; /* D6 @ P3.6 */
    _WDWORD(0x4002C19C, _RDWORD(0x4002C19C) | 0x1);           // LPC_IOCON->P3_7 |= 1; /* D7 @ P3.7 */
    _WDWORD(0x4002C1A0, _RDWORD(0x4002C1A0) | 0x1);           // LPC_IOCON->P3_8 |= 1; /* D8 @ P3.8 */
    _WDWORD(0x4002C1A4, _RDWORD(0x4002C1A4) | 0x1);           // LPC_IOCON->P3_9 |= 1; /* D9 @ P3.9 */
    _WDWORD(0x4002C1A8, _RDWORD(0x4002C1A8) | 0x1);           // LPC_IOCON->P3_10 |= 1; /* D10 @ P3.10 */
    _WDWORD(0x4002C1AC, _RDWORD(0x4002C1AC) | 0x1);           // LPC_IOCON->P3_11 |= 1; /* D11 @ P3.11 */
    _WDWORD(0x4002C1B0, _RDWORD(0x4002C1B0) | 0x1);           // LPC_IOCON->P3_12 |= 1; /* D12 @ P3.12 */
    _WDWORD(0x4002C1B4, _RDWORD(0x4002C1B4) | 0x1);           // LPC_IOCON->P3_13 |= 1; /* D13 @ P3.13 */
    _WDWORD(0x4002C1B8, _RDWORD(0x4002C1B8) | 0x1);           // LPC_IOCON->P3_14 |= 1; /* D14 @ P3.14 */
    _WDWORD(0x4002C1BC, _RDWORD(0x4002C1BC) | 0x1);           // LPC_IOCON->P3_15 |= 1; /* D15 @ P3.15 */
    _WDWORD(0x4002C1C0, _RDWORD(0x4002C1C0) | 0x1);           // LPC_IOCON->P3_16 |= 1; /* D16 @ P3.16 */
    _WDWORD(0x4002C1C4, _RDWORD(0x4002C1C4) | 0x1);           // LPC_IOCON->P3_17 |= 1; /* D17 @ P3.17 */
    _WDWORD(0x4002C1C8, _RDWORD(0x4002C1C8) | 0x1);           // LPC_IOCON->P3_18 |= 1; /* D18 @ P3.18 */
    _WDWORD(0x4002C1CC, _RDWORD(0x4002C1CC) | 0x1);           // LPC_IOCON->P3_19 |= 1; /* D19 @ P3.19 */
    _WDWORD(0x4002C1D0, _RDWORD(0x4002C1D0) | 0x1);           // LPC_IOCON->P3_20 |= 1; /* D20 @ P3.20 */
    _WDWORD(0x4002C1D4, _RDWORD(0x4002C1D4) | 0x1);           // LPC_IOCON->P3_21 |= 1; /* D21 @ P3.21 */
    _WDWORD(0x4002C1D8, _RDWORD(0x4002C1D8) | 0x1);           // LPC_IOCON->P3_22 |= 1; /* D22 @ P3.22 */
    _WDWORD(0x4002C1DC, _RDWORD(0x4002C1DC) | 0x1);           // LPC_IOCON->P3_23 |= 1; /* D23 @ P3.23 */
    _WDWORD(0x4002C1E0, _RDWORD(0x4002C1E0) | 0x1);           // LPC_IOCON->P3_24 |= 1; /* D24 @ P3.24 */
    _WDWORD(0x4002C1E4, _RDWORD(0x4002C1E4) | 0x1);           // LPC_IOCON->P3_25 |= 1; /* D25 @ P3.25 */
    _WDWORD(0x4002C1E8, _RDWORD(0x4002C1E8) | 0x1);           // LPC_IOCON->P3_26 |= 1; /* D26 @ P3.26 */
    _WDWORD(0x4002C1EC, _RDWORD(0x4002C1EC) | 0x1);           // LPC_IOCON->P3_27 |= 1; /* D27 @ P3.27 */
    _WDWORD(0x4002C1F0, _RDWORD(0x4002C1F0) | 0x1);           // LPC_IOCON->P3_28 |= 1; /* D28 @ P3.28 */
    _WDWORD(0x4002C1F4, _RDWORD(0x4002C1F4) | 0x1);           // LPC_IOCON->P3_29 |= 1; /* D29 @ P3.29 */
    _WDWORD(0x4002C1F8, _RDWORD(0x4002C1F8) | 0x1);           // LPC_IOCON->P3_30 |= 1; /* D30 @ P3.30 */
    _WDWORD(0x4002C1FC, _RDWORD(0x4002C1FC) | 0x1);           // LPC_IOCON->P3_31 |= 1; /* D31 @ P3.31 */
    _WDWORD(0x4002C200, _RDWORD(0x4002C200) | 0x1);           // LPC_IOCON->P4_0 |= 1; /* A0 @ P4.0 */
    _WDWORD(0x4002C204, _RDWORD(0x4002C204) | 0x1);           // LPC_IOCON->P4_1 |= 1; /* A1 @ P4.1 */
    _WDWORD(0x4002C208, _RDWORD(0x4002C208) | 0x1);           // LPC_IOCON->P4_2 |= 1; /* A2 @ P4.2 */
    _WDWORD(0x4002C20C, _RDWORD(0x4002C20C) | 0x1);           // LPC_IOCON->P4_3 |= 1; /* A3 @ P4.3 */
    _WDWORD(0x4002C210, _RDWORD(0x4002C210) | 0x1);           // LPC_IOCON->P4_4 |= 1; /* A4 @ P4.4 */
    _WDWORD(0x4002C214, _RDWORD(0x4002C214) | 0x1);           // LPC_IOCON->P4_5 |= 1; /* A5 @ P4.5 */
    _WDWORD(0x4002C218, _RDWORD(0x4002C218) | 0x1);           // LPC_IOCON->P4_6 |= 1; /* A6 @ P4.6 */
    _WDWORD(0x4002C21C, _RDWORD(0x4002C21C) | 0x1);           // LPC_IOCON->P4_7 |= 1; /* A7 @ P4.7 */
    _WDWORD(0x4002C220, _RDWORD(0x4002C220) | 0x1);           // LPC_IOCON->P4_8 |= 1; /* A8 @ P4.8 */
    _WDWORD(0x4002C224, _RDWORD(0x4002C224) | 0x1);           // LPC_IOCON->P4_9 |= 1; /* A9 @ P4.9 */
    _WDWORD(0x4002C228, _RDWORD(0x4002C228) | 0x1);           // LPC_IOCON->P4_10 |= 1; /* A10 @ P4.10 */
    _WDWORD(0x4002C22C, _RDWORD(0x4002C22C) | 0x1);           // LPC_IOCON->P4_11 |= 1; /* A11 @ P4.11 */
    _WDWORD(0x4002C230, _RDWORD(0x4002C230) | 0x1);           // LPC_IOCON->P4_12 |= 1; /* A12 @ P4.12 */
    _WDWORD(0x4002C234, _RDWORD(0x4002C234) | 0x1);           // LPC_IOCON->P4_13 |= 1; /* A13 @ P4.13 */
    _WDWORD(0x4002C238, _RDWORD(0x4002C238) | 0x1);           // LPC_IOCON->P4_14 |= 1; /* A14 @ P4.14 */
    _WDWORD(0x4002C23C, _RDWORD(0x4002C23C) | 0x1);           // LPC_IOCON->P4_15 |= 1; /* A15 @ P4.15 */
    _WDWORD(0x4002C240, _RDWORD(0x4002C240) | 0x1);           // LPC_IOCON->P4_16 |= 1; /* A16 @ P4.16 */
    _WDWORD(0x4002C244, _RDWORD(0x4002C244) | 0x1);           // LPC_IOCON->P4_17 |= 1; /* A17 @ P4.17 */
    _WDWORD(0x4002C248, _RDWORD(0x4002C248) | 0x1);           // LPC_IOCON->P4_18 |= 1; /* A18 @ P4.18 */
    _WDWORD(0x4002C24C, _RDWORD(0x4002C24C) | 0x1);           // LPC_IOCON->P4_19 |= 1; /* A19 @ P4.19 */
    _WDWORD(0x4002C250, _RDWORD(0x4002C250) | 0x1);           // LPC_IOCON->P4_20 |= 1; /* A20 @ P4.20 */
    _WDWORD(0x4002C254, _RDWORD(0x4002C254) | 0x1);           // LPC_IOCON->P4_21 |= 1; /* A21 @ P4.21 */
    _WDWORD(0x4002C258, _RDWORD(0x4002C258) | 0x1);           // LPC_IOCON->P4_22 |= 1; /* A22 @ P4.22 */
    _WDWORD(0x4002C25C, _RDWORD(0x4002C25C) | 0x1);           // LPC_IOCON->P4_23 |= 1; /* A23 @ P4.23 */
    _WDWORD(0x4002C260, _RDWORD(0x4002C260) | 0x1);           // LPC_IOCON->P4_24 |= 1; /* OEN @ P4.24 */
    _WDWORD(0x4002C264, _RDWORD(0x4002C264) | 0x1);           // LPC_IOCON->P4_25 |= 1; /* WEN @ P4.25 */
    _WDWORD(0x4002C268, _RDWORD(0x4002C268) | 0x1);           // LPC_IOCON->P4_26 |= 1; /* BLSN[0] @ P4.26 */
    _WDWORD(0x4002C26C, _RDWORD(0x4002C26C) | 0x1);           // LPC_IOCON->P4_27 |= 1; /* BLSN[1] @ P4.27 */
    _WDWORD(0x4002C270, _RDWORD(0x4002C270) | 0x1);           // LPC_IOCON->P4_28 |= 1; /* BLSN[2] @ P4.28 */
    _WDWORD(0x4002C274, _RDWORD(0x4002C274) | 0x1);           // LPC_IOCON->P4_29 |= 1; /* BLSN[3] @ P4.29 */
    _WDWORD(0x4002C278, _RDWORD(0x4002C278) | 0x1);           // LPC_IOCON->P4_30 |= 1; /* CSN[0] @ P4.30 */
    _WDWORD(0x4002C27C, _RDWORD(0x4002C27C) | 0x1);           // LPC_IOCON->P4_31 |= 1; /* CSN[1] @ P4.31 */
    _WDWORD(0x4002C138, _RDWORD(0x4002C138) | 0x1);           // LPC_IOCON->P2_14 |= 1; /* CSN[2] @ P2.14 */
    _WDWORD(0x4002C13C, _RDWORD(0x4002C13C) | 0x1);           // LPC_IOCON->P2_15 |= 1; /* CSN[3] @ P2.15 */

    _WDWORD(PCONP_REG,      _RDWORD(PCONP_REG) | 0x00000800);   // LPC_SC->PCONP |= 0x00000800;

    //*********************************************
    // DYNAMIC MEMORY CONFIGURATION
    //*********************************************
    _WDWORD(EMCDLYCTL_REG,      0x00000A05);                    //LPC_SC->EMCDLYCTL   = 0x00000A05;

    _WDWORD(EMC_CTRL_REG,   0x1);                               // LPC_EMC->Control = 0x00000001;
    _WDWORD(EMC_CONFIG_REG, 0x0);                               // LPC_EMC->Config = 0x00000000;

    _WDWORD(SCS_REG,        _RDWORD(SCS_REG) | (1<<1));        //LPC_SC->SCS |= (1<<1);
    _WDWORD(SCS_REG,        _RDWORD(SCS_REG) & ~(0x00000001)); //LPC_SC->SCS &= ~(0x00000001);

    _WDWORD(EMC_DYN_CFG0_REG,   0x00001680);    //LPC_EMC->DynamicConfig0 = 0x00001680;
    _WDWORD(EMCDLYCTL_REG,      0x00000A05);

    _WDWORD(EMC_DYN_RASCAS0_REG, 2 + (2<<8));   //LPC_EMC->DynamicRasCas0 = RAS_Latency + (CAS_Latency<<8);

    _WDWORD(EMC_DYN_RD_CFG_REG, 0x00000001);        //LPC_EMC->DynamicReadConfig = 0x00000001;

    _WDWORD(EMC_DYN_RP_REG,     NS_2_CLKS(18));     //LPC_EMC->DynamicRP   = NS_2_CLKS(18);
    _WDWORD(EMC_DYN_RAS_REG,    NS_2_CLKS(42));     //LPC_EMC->DynamicRAS = NS_2_CLKS(42);
    _WDWORD(EMC_DYN_SREX_REG,   NS_2_CLKS(70));     //LPC_EMC->DynamicSREX = NS_2_CLKS(70);
    _WDWORD(EMC_DYN_APR_REG,    NS_2_CLKS(18));     //LPC_EMC->DynamicAPR = NS_2_CLKS(18);
    _WDWORD(EMC_DYN_DAL_REG,    4);                 //LPC_EMC->DynamicDAL = CAS_Latency+2;
    _WDWORD(EMC_DYN_WR_REG,     (NS_2_CLKS(6)+1)); //LPC_EMC->DynamicWR   = (NS_2_CLKS(6)+1);
    _WDWORD(EMC_DYN_RC_REG,     NS_2_CLKS(60));     //LPC_EMC->DynamicRC   = NS_2_CLKS(60);
    _WDWORD(EMC_DYN_RFC_REG,    NS_2_CLKS(60));     //LPC_EMC->DynamicRFC = NS_2_CLKS(60);
    _WDWORD(EMC_DYN_XSR_REG,    NS_2_CLKS(70));     //LPC_EMC->DynamicXSR = NS_2_CLKS(70);
    _WDWORD(EMC_DYN_RRD_REG,    NS_2_CLKS(12));     //LPC_EMC->DynamicRRD = NS_2_CLKS(12);
    _WDWORD(EMC_DYN_MRD_REG,    2);                 //LPC_EMC->DynamicMRD = 2;

    _WDWORD(EMC_DYN_CTRL_REG,   0x00000183);        //LPC_EMC->DynamicControl = 0x00000183;

    _sleep_(2);

    _WDWORD(EMC_DYN_CTRL_REG,   0x00000183);        //LPC_EMC->DynamicControl = 0x00000183;

    _sleep_(2);

    _WDWORD(EMC_DYN_CTRL_REG,   0x00000103);        //LPC_EMC->DynamicControl = 0x00000103;
    _WDWORD(EMC_DYN_RFSH_REG,   0x00000001);        //LPC_EMC->DynamicRefresh = 0x00000001; // 1 x 16 = 16 CCLKs between SDRAM refresh cycles

    _sleep_(2);

    _WDWORD(EMC_DYN_CTRL_REG,   0x00000103);        //LPC_EMC->DynamicControl = 0x00000103;
    _WDWORD(EMC_DYN_RFSH_REG,   0x00000001);        //LPC_EMC->DynamicRefresh = 0x00000001; // 1 x 16 = 16 CCLKs between SDRAM refresh cycles

    _sleep_(2);

    _WDWORD(EMC_DYN_RFSH_REG,   NS_2_CLKS(7813 + 1)>>4); //LPC_EMC->DynamicRefresh = NS_2_CLKS(7813 + 1)>>4;     // Refresh units are x16 (8192 rows...)

    _sleep_(1);

    _WDWORD(EMC_DYN_CTRL_REG,   0x00000083);        //LPC_EMC->DynamicControl    = 0x00000083; /* Issue MODE command */

    _RDWORD(SDRAM_BASE_ADDR|((0x03+(2<<4))<<10));   //Temp = *((volatile uint32_t *)(SDRAM_BASE_ADDR|((0x03+(CAS_Latency<<4))<<10)));

    _sleep_(1);

    _WDWORD(EMC_DYN_CTRL_REG,    0x00000000);        //LPC_EMC->DynamicControl = 0x00000000;
    _WDWORD(EMC_DYN_CFG0_REG,    _RDWORD(EMC_DYN_CFG0_REG) | 0x00080000);    //LPC_EMC->DynamicConfig0 |= 0x00080000;

    //*********************************************
    // STATIC MEMORY CONFIGURATION
    //*********************************************
    _WDWORD(EMC_STA_CFG0_REG,   0x00000081);    // LPC_EMC->StaticConfig0   = 0x00000081;
    _WDWORD(EMC_STA_WWEN0_REG, 0x00000003);    // LPC_EMC->StaticWaitWen0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
    _WDWORD(EMC_STA_WOEN0_REG, 0x00000003);    // LPC_EMC->StaticWaitOen0 = 0x00000003; /* ( n     ) -> 0 clock cycles */
    _WDWORD(EMC_STA_WRD0_REG,   0x00000006);    // LPC_EMC->StaticWaitRd0   = 0x00000006; /* ( n + 1 ) -> 7 clock cycles */
    _WDWORD(EMC_STA_WPAGE0_REG, 0x00000003);    // LPC_EMC->StaticWaitPage0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
    _WDWORD(EMC_STA_WWR0_REG,   0x00000005);    // LPC_EMC->StaticWaitWr0   = 0x00000005; /* ( n + 2 ) -> 7 clock cycles */
    _WDWORD(EMC_STA_WTURN0_REG, 0x00000003);    // LPC_EMC->StaticWaitTurn0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */

    _sleep_(100);
}

define button "init_emc()", "init_emc()";

Setup();
init_emc();
//G,SystemInit;
//init_emc();
G;
</code>

Re: problem with EMC LPC1788

lpcware — Wed, 15 Jun 2016 17:44:48 GMT

Content originally posted in LPCWare by kickoune on Tue Dec 20 03:59:32 MST 2011
thanks, i will try to use your .INI file.

good day!

Re: problem with EMC LPC1788

lpcware — Wed, 15 Jun 2016 17:44:49 GMT

Content originally posted in LPCWare by kickoune on Wed Dec 21 01:21:45 MST 2011
thanks you for your reply.
Have you a "const" declared in your external flash for use .INI file?

Re: problem with EMC LPC1788

lpcware — Wed, 15 Jun 2016 17:44:49 GMT

Content originally posted in LPCWare by samwong44 on Sun Mar 18 22:48:53 MST 2012
Hi,

I using LPC1778 connect to external NOR Flash MX29GL512E and configure the hardware and firmware as below but not work (even read a manufacturer code also return incorrect data)
If using the same code run in LPC2468 no problem (different is with byte lane enable), anyone can help me check what is the mistake on this?

Hardware connection:
A1~A25 (MCU) <>A0~A24 (NOR)
D0~D15 (MCU) <>D0~D15 (NOR)
/RSTOUT (MCU) <> /RESET(NOR)
/WE (MCU) <> /WE(NOR)
/CS0 (MCU) <> /CE(NOR)
/OE (MCU) <> /OE(NOR)
/BYTE (NOR) = High (Word mode)

Firmware:
#define NORFLASHADDRATIO 2
#define NORFLASH_CMD_LATCH1_OFFSET 0x555 //command latch 1
#define NORFLASH_CMD_LATCH2_OFFSET 0x2AA //command latch 2
#define NORFLASH_CMD_LATCH1 NORFLASH_BASE + (NORFLASH_CMD_LATCH1_OFFSET*NORFLASHADDRATIO)
#define NORFLASH_CMD_LATCH2 NORFLASH_BASE + (NORFLASH_CMD_LATCH2_OFFSET*NORFLASHADDRATIO)

#define MANUFACTURERID_ADDR NORFLASH_BASE + (0x00*NORFLASHADDRATIO)
#define DEVICEID1_ADDR NORFLASH_BASE + (0x01*NORFLASHADDRATIO)
#define DEVICEID2_ADDR NORFLASH_BASE + (0x0E*NORFLASHADDRATIO)
#define DEVICEID3_ADDR NORFLASH_BASE + (0x0F*NORFLASHADDRATIO)

#define NORFLASH_CMD_UNLOCK1 0x00AA //command for unlock cycle 1
#define NORFLASH_CMD_UNLOCK2 0x0055 //command for unlock cycle 2
#define NORFLASH_CMD_AUTOSELECT 0x0090 //command for going into Autoselect mode

void EMC_init()
{
PCONP_REG |= 0x100000000000; //enable EMC power

IOCON_P4_01_REG=0x31; //EMC address: A1~A25
IOCON_P4_01_REG=0x31;
...
IOCON_P4_23_REG=0x31;
IOCON_P5_00_REG=0x31;
IOCON_P5_01_REG=0x31;
IOCON_P3_00_REG=0x31; //EMC data: D0~D15
IOCON_P3_01_REG=0x31;
...
IOCON_P3_15_REG=0x31;
IOCON_P4_24_REG=0x31; //EMC OE
IOCON_P4_25_REG=0x31; //EMC WE
IOCON_P4_30_REG=0x31; //EMC CS0

EMCConfig=0x00; //little endian
EMCStaticConfig0=0x01;
//16bit,page mode disable,active low CS,byte lane disable,
//extended wait disable,buffer disable, no write protect
EMCSTA_WWEN0=0x0e; //Static Memory Write Enable Delay registers setting
EMCSTA_WOEN0=0x0e; //Static Memory Output Enable Delay registers setting
EMCSTA_WRD0=0x01e; //Static Memory Read Delay registers setting//read access delay
EMCSTA_WPAGE0=0x01e; //Static Memory Page Mode Read Delay
EMCSTA_WWR0 =0x0e; //Static Memory Write Delay registers setting//write access delay
EMCSTA_WT0=0x0e; //Static Memory Turn Round Delay registers
EMCDLYCTL_REG=0X0a0a0a0e; //EMC delay control register
EMCCLKSEL_REG|=1; //EMC clock=half rate of CPU

EMCControl=0x01;
}

void NOR_init()
{
ptrNORAddress =(void*)NORFLASH_CMD_LATCH1;
*ptrNORAddress = NORFLASH_CMD_UNLOCK1;
ptrNORAddress =(void*)NORFLASH_CMD_LATCH2;
*ptrNORAddress = NORFLASH_CMD_UNLOCK2;
ptrNORAddress =(void*)NORFLASH_CMD_LATCH1;
*ptrNORAddress = NORFLASH_CMD_AUTOSELECT;

ptrNORAddress =(unsigned long*)MANUFACTURERID_ADDR;
usNORData = *ptrNORAddress; //read manufacturer code fail, should return usNORDate=0xC2
}