topic Re: Peripheral SRAM in LPC Microcontrollers

Peripheral SRAM

lpcware — Wed, 15 Jun 2016 17:46:13 GMT

Content originally posted in LPCWare by ezharkov on Fri Aug 30 11:18:10 MST 2013
From UM10470:
0x2000 0000 - 0x2000 1FFF Peripheral SRAM - bank 0 (first 8 kB)
0x2000 2000 - 0x2000 3FFF Peripheral SRAM - bank 0 (second 8 kB)
0x2000 4000 - 0x2000 7FFF Peripheral SRAM - bank 1 (16 kB)

Why the difference between bank 0 and bank 1? Why bank 0 is split into the "first" and "second" 8kB? Are those two 8kB sections on different ports or something?

Will a DMA transaction work with a block that starts in the first 8k and ends in the second 8k?
Will a DMA transaction work with a block that starts in the bank 0 and ends in the bank 1?

Thanks,
Eugene

Re: Peripheral SRAM

lpcware — Wed, 15 Jun 2016 17:46:14 GMT

Content originally posted in LPCWare by usb10185 on Fri Aug 30 12:48:15 MST 2013
Hi,

The DMA should work across the boundaries assuming that the addressing is contiguous.
The UM Figure 2 explains why there are different banks of SRAM - It allows for multi-master access to different banks without memory contention.

Thanks,
Ken

Re: Peripheral SRAM

lpcware — Wed, 15 Jun 2016 17:46:14 GMT

Content originally posted in LPCWare by ezharkov on Fri Aug 30 13:03:40 MST 2013
Figure 2 shows two 16 kB banks, bank 0 and bank 1, I presume. They are on different ports, and that eliminates contention. I understand that. But my question was about the two 8 kB sections in the bank 0. Why are they documented as two separate 8 kB sections instead of one single 16 kB, like bank 1?

Re: Peripheral SRAM

lpcware — Wed, 15 Jun 2016 17:46:16 GMT

Content originally posted in LPCWare by usb10185 on Fri Aug 30 15:31:18 MST 2013
Hi,

The LPC1774 is a 40KB part in this family so the memory map is represented in this way.

Thanks,
Ken