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    <title>LPC MicrocontrollersのトピックRe: LPC18xx SDMMC, ACMD51 or CMD6 Reply</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948459#M37697</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I checked registers descripton again and it seems that I do not need BLKSIZ and BYTCNT at all.&lt;/P&gt;&lt;P&gt;Because reading 8 bytes - it is not a block tranfer.&lt;/P&gt;&lt;P&gt;So I guess that I need antoher way how to tell MCI amount of bytes to receive.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Antoher question is that in user manual DATA register is described (&amp;gt;= @0x40004100), but there is no such address in CMSIS library :smileysad:&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 21 Aug 2019 09:11:15 GMT</pubDate>
    <dc:creator>romanleonov</dc:creator>
    <dc:date>2019-08-21T09:11:15Z</dc:date>
    <item>
      <title>LPC18xx SDMMC, ACMD51 or CMD6 Reply</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948458#M37696</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi!&lt;/P&gt;&lt;P&gt;I&amp;nbsp;try&amp;nbsp;to get SD Configuration register answer (ACMD51) or SWITCH CONFIG (CMD6) reply on LPC18xx (LPC1822, LPC1837 or LPC43xx, all the same).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unfortunatelly, I have a problem here, because 512 bytes of data (READ/WRITE SINGLE BLOCK) works well for me.&lt;/P&gt;&lt;P&gt;But when I try to get less data than 512 bytes "Data Transfer Over" Interrupt not follow then.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, I set BLKSIZ, FIFOTH and BYTCNT registers to get 8 bytes (64 bits) reply for SD configuration register.&amp;nbsp;&lt;/P&gt;&lt;P&gt;And I can see reply throw analyzer, but there is no IRQ then in my software. So I can't get reply data from FIFO.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here my settings:&lt;/P&gt;&lt;P&gt;LPC_SDMMC-&amp;gt;BLKSIZ = 1; // 1 byte for block&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* RX_WMark = 0, TX_WMark = 15 (doesn't matter in rx mode i think) and MSize = 1 transfer */&lt;/P&gt;&lt;P&gt;LPC_SDMMC-&amp;gt;FIFOTH = (15 &amp;lt;&amp;lt; SDMMC_FIFOTH_TX_WMARK_Pos) |&amp;nbsp;&lt;BR /&gt;(0 &amp;lt;&amp;lt; SDMMC_FIFOTH_RX_WMARK_Pos) |&amp;nbsp;&lt;BR /&gt; SDMMC_FIFOTH_DMA_MTS_1;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* then i configure sdmmc descriptor to receive 8 bytes of data. One chain descriptor */&lt;/P&gt;&lt;P&gt;LPC_SDMMC-&amp;gt;BYTCNT = 8; // 8 bytes for recieption&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* then i send ACMD51 command */&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88903iBEE5CF0335B2500E/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;But there is no IRQ.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does someone tryed to get reply&amp;nbsp;for ACMD51 or CMD6 sdmmc command on LPC18xx?&lt;/P&gt;&lt;P&gt;Maybe without DMA, just read data straight from FIFO.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 20 Aug 2019 16:32:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948458#M37696</guid>
      <dc:creator>romanleonov</dc:creator>
      <dc:date>2019-08-20T16:32:34Z</dc:date>
    </item>
    <item>
      <title>Re: LPC18xx SDMMC, ACMD51 or CMD6 Reply</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948459#M37697</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I checked registers descripton again and it seems that I do not need BLKSIZ and BYTCNT at all.&lt;/P&gt;&lt;P&gt;Because reading 8 bytes - it is not a block tranfer.&lt;/P&gt;&lt;P&gt;So I guess that I need antoher way how to tell MCI amount of bytes to receive.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Antoher question is that in user manual DATA register is described (&amp;gt;= @0x40004100), but there is no such address in CMSIS library :smileysad:&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Aug 2019 09:11:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948459#M37697</guid>
      <dc:creator>romanleonov</dc:creator>
      <dc:date>2019-08-21T09:11:15Z</dc:date>
    </item>
    <item>
      <title>Re: LPC18xx SDMMC, ACMD51 or CMD6 Reply</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948460#M37698</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I discovered that I got DU interrupt if I had disabled OWN bit in DMA Descriptor&amp;nbsp;during&amp;nbsp;READ SINGLE BLOCK COMMAND.&lt;/P&gt;&lt;P&gt;But when I do the same with 64 bytes read of CMD6 reply interrupt DU does not occure.&lt;/P&gt;&lt;P&gt;Seems that DMA doesn't try to initiate receiption at all.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Research in process ...&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Aug 2019 10:19:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948460#M37698</guid>
      <dc:creator>romanleonov</dc:creator>
      <dc:date>2019-08-21T10:19:23Z</dc:date>
    </item>
    <item>
      <title>Re: LPC18xx SDMMC, ACMD51 or CMD6 Reply</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948461#M37699</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Finally, I've solved the problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1) Command ACMD51 amd CMD6 are commands with data. So wee need to set&amp;nbsp;DATA_EXPECTED bit in CMD register. Otherwise DMA wouldn't try to receive any data and we haven't IRQ DU, as I wrote before. That's why.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2) After settings this bit, we can check RINTSTS register to NIS flag.&amp;nbsp;&lt;/P&gt;&lt;P&gt;3) BYTSIZ and FIFOTH doesn't influence. So it could be the same as to READ SINGLE BLOCK command.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here is my list of actions:&lt;/P&gt;&lt;P&gt;/* BLKSIZ */&lt;/P&gt;&lt;P&gt;LPC_SDMMC-&amp;gt;BLKSIZ = sd_sector_size; // 512, no problem it's OK&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* setup descriptor for data reception */&lt;/P&gt;&lt;P&gt;sdmmc.descr[0].buf1 = data; // some pointer, 32 aligned&lt;BR /&gt;sdmmc.descr[0].buf2 = NULL; // one chain descriptor&lt;BR /&gt; /* set size */&lt;BR /&gt;sdmmc.descr[0].size = (size &amp;lt;&amp;lt; SDMMC_DESC1_BS1_Pos) &amp;amp; SDMMC_DESC1_BS1_Msk; // size - 8 bytes for ACMD51 and 64 bytes for CMD6.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; /* first descriptor and last, own by dma */&lt;BR /&gt;sdmmc.descr[0].ctl = SDMMC_DESC0_FS_Msk | SDMMC_DESC0_CH_Msk | SDMMC_DESC0_OWN_Msk | SDMMC_DESC0_LD_Msk;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* setup size */&lt;BR /&gt; LPC_SDMMC-&amp;gt;BYTCNT = size;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* send cmd */&lt;/P&gt;&lt;P&gt;sdmmc_cmd(SDMMC_CMD_SWITCH_FUNC, (CF_MODE_CHECK &amp;lt;&amp;lt; CF_MODE_OFFS) | 0xFFFFFF, &amp;amp;resp, SDMMC_NO_RESPONSE); // my implementation with cmd reg fill and send cmd to card, verify answer and so on ...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* wait DMA flag */&lt;/P&gt;&lt;P&gt;while((LPC_SDMMC-&amp;gt;IDSTS &amp;amp; SDMMC_IDSTS_NIS_Msk) == 0)); // possible improve with timeout, but OK&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* now we can extract or parse data from data buffer */&lt;/P&gt;&lt;P&gt;...&lt;/P&gt;&lt;P&gt;/* here is my example of switch function reply */&lt;/P&gt;&lt;P&gt;max current: 50 mA&lt;BR /&gt;group 6: 8001&lt;BR /&gt;group 5: 8001&lt;BR /&gt;group 4: 8001&lt;BR /&gt;group 3: 8001&lt;BR /&gt;group 2: 8001&lt;BR /&gt;group 1: 8003&lt;BR /&gt;group 6 mode: 0&lt;BR /&gt;group 5 mode: 0&lt;BR /&gt;group 4 mode: 0&lt;BR /&gt;group 3 mode: 0&lt;BR /&gt;group 2 mode: 0&lt;BR /&gt;group 1 mode: 1&lt;BR /&gt;ds version: 0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For more information I used&amp;nbsp;Physical Layer SD Specification Version 3.00 from SD Group. CMD6 reply data is described "4.3.10.4 Switch Function Statuson",&amp;nbsp; page 52.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope, someone find this topic helpfull or interesting at least.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 22 Aug 2019 10:17:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC18xx-SDMMC-ACMD51-or-CMD6-Reply/m-p/948461#M37699</guid>
      <dc:creator>romanleonov</dc:creator>
      <dc:date>2019-08-22T10:17:51Z</dc:date>
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