topic Re: Issue initializing USBFSD on LPC55S69 in LPC Microcontrollers

Issue initializing USBFSD on LPC55S69

nickray — Wed, 18 Sep 2019 22:41:38 GMT

I'm trying to write a Rust USB FS device driver for the LPC55S6x chips, using the LPC55S69-EVK board.

I'm using gdb to connect via JLinkGDBServer to a J-Link OB.

Following section 41.3 of UM11126, I'm trying to set DEV_ENABLE in the USBFSH PortMode register. This fails, and I can't even read out the value of this bit. Instead JLinkGDBServer starts losing connection to the device.

Is there any known reason why reading and writing the portmode might fail? Possibly some detail specific to the EVK board?

To make matters worse, I can no longer connect at all:

Connecting to target...ERROR: InitTarget(): PCode returned with error code -1
ERROR: Could not connect to target.

And even mass erasing flash via JFlashLite with J10 set fails.

So while I wait for a replacement board, any pointers are very much appreciated.

Re: Issue initializing USBFSD on LPC55S69

FelipeGarcia — Fri, 20 Sep 2019 21:16:35 GMT

Hi Nicolas,

Regarding the debug access I recommend you to check the following post and try booting into ISP mode.

Regaining debug access to target MCU

Regarding the PortMode register issue, please make sure you turn on the USB PHY in PDRUNCFG0 register. Also you need to Enable port mode configuration by setting the USB0_HOSTS in the AHBCLKCTRL2 register.

I recommend you to check our examples from the SDK so you have a better approach to what you need to do in order to implement your own USB driver. You can download the SDK from the following link.

Welcome | MCUXpresso SDK Builder

Hope it helps!

Best regards,

Felipe

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Re: Issue initializing USBFSD on LPC55S69

nickray — Sat, 21 Sep 2019 23:23:12 GMT

I managed to solve my issue: USB0CLKDIV.HALT needs to be cleared.

- when using the 96MHz clock, flash wait cycles need to be set to 8 via the field FMCTIM in the register FMCCR of SYSCON.

- very much harder figure out for me was that USB0CLKDIV has a reset HALT value of 1 (not running), this needs to be explicitly cleared. The CLOCK_SetClkDiv function in the sample code manages to hide this quite well!! As it has a code path that explicitly sets the bit, vs implicitly clearing it when assigning "divisor minus one". Since I use a register-access layer generated from the SVD, this was completely non-obvious to me.