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    <title>topic Re: Read ADC with DMA LPC1758 in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Read-ADC-with-DMA-LPC1758/m-p/520662#M3756</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;bump&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 19 Jun 2016 01:11:45 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-19T01:11:45Z</dc:date>
    <item>
      <title>Read ADC with DMA LPC1758</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Read-ADC-with-DMA-LPC1758/m-p/520661#M3755</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by andrea.giuffrida1 on Wed May 25 05:37:12 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello everybody!&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm trying to read three ADC channel with DMA.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;If I disable the DMA controller the ADC works correctly but i don't understand where is the error in the DMA code.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Could someone help me to find the error?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;volatile uint32_t ADCBuff[3] = {0,0,0};&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;void initDMA(void) {&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMA-&amp;gt;DMACConfig = 0; /* Disable DMA */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMA-&amp;gt;DMACIntTCClear |= 0xFF;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMA-&amp;gt;DMACIntErrClr |= 0xFF;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH0-&amp;gt;DMACCLLI = (unsigned int)(LPC_GPDMACH1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH0-&amp;gt;DMACCSrcAddr = (unsigned int)&amp;amp;(LPC_ADC-&amp;gt;ADDR3);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH0-&amp;gt;DMACCDestAddr = (unsigned int)ADCBuff;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH0-&amp;gt;DMACCControl = (1u &amp;lt;&amp;lt; 0 )|/* TransferSize */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(0u &amp;lt;&amp;lt; 12)|/* Source Burst Size */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(0u &amp;lt;&amp;lt; 15)|/* Dest Burst Size */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 18)|/* Source transfer width = 32bit */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 21)|/* Dest transfer width = 32bit */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 27)|/* the destination address is incremented after each transfer */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 31);/* the terminal count interrupt is enabled. */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH0-&amp;gt;DMACCConfig = (1u &amp;lt;&amp;lt; 0)|/* Channel enabled */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(4u &amp;lt;&amp;lt; 1)|/* SrcPeripheral ADC */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 11)|/* Transfer Type Periph to Memory */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 14)|/* IE Mask */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 15);/* ITC Mask */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH1-&amp;gt;DMACCLLI = (unsigned int)(LPC_GPDMACH2);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH1-&amp;gt;DMACCSrcAddr = (unsigned int)&amp;amp;(LPC_ADC-&amp;gt;ADDR6);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH1-&amp;gt;DMACCDestAddr = (unsigned int)(ADCBuff + 1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH1-&amp;gt;DMACCControl = (1u &amp;lt;&amp;lt; 0 )|/* TransferSize */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(0u &amp;lt;&amp;lt; 12)|/* Source Burst Size */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(0u &amp;lt;&amp;lt; 15)|/* Dest Burst Size */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 18)|/* Source transfer width = 32bit */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 21)|/* Dest transfer width = 32bit */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 27)|/* the destination address is incremented after each transfer */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 31);/* the terminal count interrupt is enabled. */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH1-&amp;gt;DMACCConfig = (1u &amp;lt;&amp;lt; 0)|/* Channel enabled */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(4u &amp;lt;&amp;lt; 1)|/* SrcPeripheral ADC */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 11)|/* Transfer Type Periph to Memory */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 14)|/* IE Mask */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 15);/* ITC Mask */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH2-&amp;gt;DMACCLLI = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH2-&amp;gt;DMACCSrcAddr = (unsigned int)&amp;amp;(LPC_ADC-&amp;gt;ADDR7);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH2-&amp;gt;DMACCDestAddr = (unsigned int)(ADCBuff + 2);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH2-&amp;gt;DMACCControl = (1u &amp;lt;&amp;lt; 0 )|/* TransferSize */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(0u &amp;lt;&amp;lt; 12)|/* Source Burst Size */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(0u &amp;lt;&amp;lt; 15)|/* Dest Burst Size */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 18)|/* Source transfer width = 32bit */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 21)|/* Dest transfer width = 32bit */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 27)|/* the destination address is incremented after each transfer */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 31);/* the terminal count interrupt is enabled. */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMACH2-&amp;gt;DMACCConfig = (1u &amp;lt;&amp;lt; 0)|/* Channel enabled */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(4u &amp;lt;&amp;lt; 1)|/* SrcPeripheral ADC */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(2u &amp;lt;&amp;lt; 11)|/* Transfer Type Periph to Memory */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 14)|/* IE Mask */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(1u &amp;lt;&amp;lt; 15);/* ITC Mask */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;NVIC_EnableIRQ(DMA_IRQn);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_GPDMA-&amp;gt;DMACConfig |= 1; /* Enable DMA */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;void DMA_IRQHandler(void){&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;NVIC_DisableIRQ(DMA_IRQn);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;if (DMA_done == 0) {&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;CSdata.VBATT = (ADCBuff[0] &amp;gt;&amp;gt; 4) &amp;amp; ADC_VALUE_MAX;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;CSdata.CSREF = (ADCBuff[1] &amp;gt;&amp;gt; 4) &amp;amp; ADC_VALUE_MAX;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;CSdata.CSOUT = (ADCBuff[2] &amp;gt;&amp;gt; 4) &amp;amp; ADC_VALUE_MAX;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_done = 1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/*----------------------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp; Function that initializes ADC&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; *----------------------------------------------------------------------------*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;void initADC (void) {&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_ADC-&amp;gt;ADCR = ( 1 &amp;lt;&amp;lt;&amp;nbsp; 3) |&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* select AD0.3 pin&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;( 1 &amp;lt;&amp;lt;&amp;nbsp; 6) |&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* select AD0.6 pin&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;( 1 &amp;lt;&amp;lt;&amp;nbsp; 7) |&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* select AD0.7 pin&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ( 1 &amp;lt;&amp;lt;&amp;nbsp; 8) |&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* ADC clock is 25MHz/(n+1)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;( 1 &amp;lt;&amp;lt; 16) | /* BURST. Remark: START bits must be 000 when BURST = 1 or conversions will not start.*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ( 1 &amp;lt;&amp;lt; 21);&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* enable ADC&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_ADC-&amp;gt;ADINTEN =&amp;nbsp; ( 0 &amp;lt;&amp;lt; 3) |/* CH.3 conversion interr dis */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;( 0 &amp;lt;&amp;lt; 6) |/* CH.6 conversion interr dis */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;( 1 &amp;lt;&amp;lt; 7);/* CH.7 conversion interr en */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_ADC-&amp;gt;ADINTEN &amp;amp;= ~(1 &amp;lt;&amp;lt; 8);/*Global Interrupt*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;NVIC_DisableIRQ(ADC_IRQn);/* Disable ADC Interrupt*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 17:45:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Read-ADC-with-DMA-LPC1758/m-p/520661#M3755</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T17:45:19Z</dc:date>
    </item>
    <item>
      <title>Re: Read ADC with DMA LPC1758</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Read-ADC-with-DMA-LPC1758/m-p/520662#M3756</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;bump&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 19 Jun 2016 01:11:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Read-ADC-with-DMA-LPC1758/m-p/520662#M3756</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-19T01:11:45Z</dc:date>
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