Hard Fault on LPC55S69 single core project

safiullah_hussa — Tue, 02 Jul 2019 13:18:39 GMT

I have a single core project where I need to turn on the capture and the match functions on timer 0.

I turn on the Capture 1 on Timer 0 and everything works fine. But as soon as I turn on the Match 1 with interrupt. I get a hard fault. When I step through the code I can't find where the hard fault is actually generated. Stepping through the code I get no hard faults.

The code is also running a USART (USART2) in polling mode to transmit some data.

/******************************************************************************
* Prototypes
*****************************************************************************/
void ctimer_capture_callback(uint32_t arg_flags);
void ctimer_match_callback(uint32_t arg_flags);

/******************************************************************************
* Global Variables
*****************************************************************************/
char g_usart2_str [256];
ctimer_config_t g_ctimer0_config, ctimer1_config;
ctimer_match_config_t ctimer0_match_config;
ctimer_match_config_t ctimer1_match_config;
usart_config_t g_usart2_config;
ctimer_callback_t g_ctimer0_callback[] = {NULL, ctimer_match_callback, NULL, NULL, NULL, ctimer_capture_callback, ctimer_capture_callback, NULL};
uint32_t g_timer0_val = 0;
uint32_t g_timer0_val_copy = 0;
uint32_t g_timer0_val_prev = 0;
uint8_t g_timer0_overflow = 0;
uint8_t g_timer0_val_valid = 0;
… Some more definitions …

/******************************************************************************
* Function Definition
*****************************************************************************/
void ctimer_capture_callback(uint32_t arg_flags)
{
CTIMER_Reset(CTIMER0);
g_timer0_val = CTIMER0->CR[1];
g_timer0_val_valid = 1;
g_printf_sig++;
}

void ctimer_match_callback(uint32_t arg_flags)
{
g_timer0_overflow++;
}
/*
* @brief Application entry point.
*/
int main(void) {

//Declarations

// Init board hardware.
    BOARD_InitBootPins();
    BOARD_InitBootClocks();
    BOARD_InitBootPeripherals();
// Init FSL debug console.
    BOARD_InitDebugConsole();

BOARD_BootClockPLL100M();

CLOCK_AttachClk(kMAIN_CLK_to_CTIMER0);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);

PRINTF("Configuring Timer 0...\n");

    const uint32_t port1_pin26_config = ( //Configure as CT_INP3
              IOCON_FUNC3 |
                                            // No addition pin function
           IOCON_MODE_PULLUP |
                                            // Standard mode, output slew rate control is enabled
                                            IOCON_PIO_SLEW_STANDARD |
                                            // Input function is not inverted
                                            IOCON_PIO_INV_DI |
                                            // Enables digital function
                                            IOCON_PIO_DIGITAL_EN |
                                            // Open drain is disabled
                                            IOCON_PIO_OPENDRAIN_DI);
    // PORT1 PIN26
    IOCON_PinMuxSet(IOCON, 1, 26, port1_pin26_config);

    const uint32_t port1_pin24_config = ( //Configure as FC2_USART_RXD
              IOCON_FUNC1 |
                                            // No addition pin function
           IOCON_MODE_INACT |
                                            // Standard mode, output slew rate control is enabled
                                            IOCON_PIO_SLEW_STANDARD |
                                            // Input function is not inverted
                                            IOCON_PIO_INV_DI |
                                            // Enables digital function
                                            IOCON_PIO_DIGITAL_EN |
                                            // Open drain is disabled
                                            IOCON_PIO_OPENDRAIN_DI);
    // PORT1 PIN24
    IOCON_PinMuxSet(IOCON, 1, 24, port1_pin24_config);

    const uint32_t port0_pin27_config = ( //Configure as FC2_USART_RXD
           IOCON_FUNC1 |
           // No addition pin function
           IOCON_MODE_INACT |
           // Standard mode, output slew rate control is enabled
           IOCON_PIO_SLEW_STANDARD |
           // Input function is not inverted
           IOCON_PIO_INV_DI |
           // Enables digital function
           IOCON_PIO_DIGITAL_EN |
           // Open drain is disabled
           IOCON_PIO_OPENDRAIN_DI);
// PORT0 PIN27
IOCON_PinMuxSet(IOCON, 0, 27, port0_pin27_config);

//Set up FLEXCOMM2 as USART2
RESET_ClearPeripheralReset(kFC2_RST_SHIFT_RSTn);

USART_GetDefaultConfig(&g_usart2_config);
g_usart2_config.baudRate_Bps = 115200U;
g_usart2_config.enableRx = true;
g_usart2_config.enableTx = true;

USART_Init(USART2, &g_usart2_config, CLOCK_GetFreq(kCLOCK_Flexcomm2));

    INPUTMUX_Init(INPUTMUX);
    INPUTMUX_AttachSignal(INPUTMUX, 1, kINPUTMUX_CtimerInp3ToTimer0Captsel);
    INPUTMUX_Deinit(INPUTMUX);

CTIMER_GetDefaultConfig(&g_ctimer0_config);
CTIMER_Init(CTIMER0, &g_ctimer0_config);

CTIMER0->CTCR &= 0x0000000F;
CTIMER0->CTCR |= ((0x2 << 5) | (1 << 4));

CTIMER_RegisterCallBack(CTIMER0, &g_ctimer0_callback[0], kCTIMER_MultipleCallback);

    // Configuration 0
    ctimer0_match_config.enableCounterReset = true;
    ctimer0_match_config.enableCounterStop = false;
    ctimer0_match_config.matchValue = 0xFFFFFFFF;
    ctimer0_match_config.outControl = kCTIMER_Output_NoAction;
    ctimer0_match_config.outPinInitState = false;
    ctimer0_match_config.enableInterrupt = true;

CTIMER_SetupMatch(CTIMER0, kCTIMER_Match_0, &ctimer0_match_config);
CTIMER_SetupCapture(CTIMER0, kCTIMER_Capture_1, kCTIMER_Capture_RiseEdge, true);

CTIMER_EnableInterrupts(CTIMER0, kCTIMER_Capture1InterruptEnable);
// CTIMER_EnableInterrupts(CTIMER0, kCTIMER_Match0InterruptEnable);

CTIMER_StartTimer(CTIMER0);

    int i = 0 ;
    /* Enter an infinite loop, just incrementing a counter. */
    while(1) {
        i++ ;

if (g_timer0_val_valid){
… Some Code ….

}

        if (i % 10000 == 0){
        sprintf(g_usart2_str, … );
        USART_WriteBlocking(USART2, (unsigned char*)(g_usart2_str), strlen(g_usart2_str));
        }

}
return 0 ;
}

I should mention that this is a semihost project.

Re: Hard Fault on LPC55S69 single core project

Sabina_Bruce — Tue, 02 Jul 2019 17:37:26 GMT

Hello Safi,

I've tried replicating the hard fault like you mentioned with no luck.

This is what I did to try to reproduce the behavior.

I'm using MCUXpresso IDE v10.3.1 [Build 2233] [2019-02-20] and the SDK Version 2.5.0.

I have imported the lpcexpresso55s69_ctimer_match_interrupt_example and used this as a base. I deleted the main source file and copied the portion you provided. I also imported the missing drivers such as the fsl_usart. I also made sure to include the proper drivers in the main source file.

Once the project was built I tried both stepping through the code(F6) and running the session (F8), but neither way caused a hard fault.

Let me know if you have any observations over what I've done so I can continue to assist you.

Best Regards,

Sabina

Re: Hard Fault on LPC55S69 single core project

safiullah_hussa — Tue, 02 Jul 2019 18:33:05 GMT

Hi Sabina,

I think I was initially wrong that it was the interrupts. I now believe it is some issue with the sprintf.

I copied the code to a no hosted project and used the sprintf and USART combo. As soon as I hit the sprintf, I get a hard fault.

I am using Newlib so I believe it should support sprintf? especially with floats?

Regards,

Safiullah Hussaini

Re: Hard Fault on LPC55S69 single core project

safiullah_hussa — Tue, 02 Jul 2019 18:58:04 GMT

No. sprintf is not the entire issue.

I noticed something.

static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};

Where FSL_FEATURE_SOC_CTIMER_COUNT = 5

This seems incorrect since callbacks should be 8 (4 for matches and 4 for captures if I am not mistaken).

Could this be a cause of the fault?

Re: Hard Fault on LPC55S69 single core project

Sabina_Bruce — Tue, 02 Jul 2019 23:27:51 GMT

I've added some sprintf and still not hardfaults.

The FSL_FEATURE_SOC_CTIMER_COUNT is regarding the number of Ctimers available.

This would be the CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4. So that number should not be changed.

When you copied the code to a different base project are you still getting a hardfault, if so are you able to detect it when you step through the code (or only if you run de debug session)?

Let me know, if so ill copy the code back(with my minor addons to test it) that you provided so you can test it out and see if the results are different.

Best Regards,

Sabina

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